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PCA9450 bảng dữ liệu(PDF) 26 Page - NXP Semiconductors |
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PCA9450 bảng dữ liệu(HTML) 26 Page - NXP Semiconductors |
26 / 96 page NXP Semiconductors PCA9450 Power management IC for i.MX 8M application processor family PCA9450 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product data sheet Rev. 1.0 — 19 November 2019 26 / 96 1. A pass-gate transistor (N-channel) that ties the ports together. 2. An output edge-rate accelerator that detects and accelerates rising edges on the I/O pins. The gate bias voltage of the pass gate transistor (T3) is set at approximately one threshold voltage above the VCC level of the low-voltage side. During a LOW-to-HIGH transition the output one-shot accelerates the output transition by switching on the PMOS transistors (T1, T2) bypassing the 10 kΩ pull-up resistors and increasing current drive capability. The one-shot is activated once the input transition reaches approximately VCCI/2; it is de-activated approximately 50 ns after the output reaches VCCO/2. During the acceleration time the driver output resistance is between approximately 50 Ω and 70 Ω. To avoid signal contention and minimize dynamic ICC, the user should wait for the one-shot circuit to turn off before applying a signal in the opposite direction. Pull-up resistors are included in the device for DC current sourcing capability. aaa-035722 GATE BIAS ONE SHOT ONE SHOT 10 kΩ A (SCLL) B (SCLH) VCCA (VINT) VCCB (SWIN) T1 T2 T3 10 kΩ Figure 19. Architecture of I2C Level translator (One channel) Each A port I/O has an internal 10 kΩ pull-up resistor to VCCA, and each B port I/O has an internal 10 kΩ pull-up resistor to VCCB. If a smaller value of pull-up resistor is required, an external resistor must be added parallel to the internal 10 kΩ, affecting the VOL level. When Level translator is disabled through I2C, the internal pull up resistors are disconnected. PCA9450 I2C Level translator is controlled by I2C register, CONFIG2 Reg. When it is configured to disabled, all I/Os assume the high-impedance OFF-state. The enable time (ten) indicates the amount of time the user must allow for one one-shot circuitry to become operational after it is enabled. 7.10 Interrupt management The IRQ_B pin is an interface to the software-controlled system that indicates any interrupt bit status change of INT1 register. The IRQ_B pin is pulled low when any unmasked interrupt bit status is changed and it is released high once application processor reads INT1 register. The INT1 bits are latched to 1 whenever corresponding STATUS1 bits are changed and the latch is cleared when the INT1 register is read. The INT1_MASK bits are used to enable or disable individual interrupt bits of INT1 register. The STATUS1 register indicates the current status and is not latched. |
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