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PCA9450 bảng dữ liệu(PDF) 23 Page - NXP Semiconductors |
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PCA9450 bảng dữ liệu(HTML) 23 Page - NXP Semiconductors |
23 / 96 page NXP Semiconductors PCA9450 Power management IC for i.MX 8M application processor family PCA9450 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved. Product data sheet Rev. 1.0 — 19 November 2019 23 / 96 aaa-035716 BUCK1, 2, 3 BUCKxOUT_DVS0 BUCK1, 2, 3 BUCKxOUT_DVS1 DVS0 : PMIC_STBY_REQ = L DVS1 : PMIC_STBY_REQ = H BUCKx Output I2C programmable Bx_DVS_PRESET 0x0C Reg L H PRESET_EN In 0x0C Reg 1 0 Min Selection BUCKxOUT_LIMIT PMIC_STBY_REQ Figure 14. DVS functional diagram The programmable voltage ramp-up and ramp-down are applied during the DVS voltage transition. The ramp rate is configured by RAMP[7:6] bits in each BUCKxCTRL registers. PMIC_STBY_REQ BUCKx DVS1 DVS0 DVS1 10us RAMP[7:6] Internal control with RAMP[7:6] BUCK output depending on Load aaa-035718 Figure 15. DVS timing 7.6.1.2 BUCK output voltage limiting Application processor may accidentally write higher voltage than absolute maximum voltage rating of its power input, which may cause significant damage on application processor. PCA9450 has registers to limit the maximum voltage to prevent such an incident. BUCK1, BUCK2 and BUCK3 maximum output are limited by BUCKxOUT_LIMIT, respectively. Even if buck output is configured to higher than the limit voltage configured in BUCKxOUT_LIMIT register, the actual buck output is clamped to the limiting voltage set by BUCKxOUT_LIMIT register. 7.6.1.3 Dual-phase configuration BUCK1 and BUCK3 are configured as dual phase buck in PCA9450C by connecting R_SNSP3_CFG pin to GND, where this dual phase buck regulator is controlled through BUCK1 registers. All BUCK3 registers are not responsive under dual-phase configuration. When R_SNSP3_CFG pin is tied to INB13 in PCA9450B, BUCK3 is disabled. BUCK1 supplies VDD_SOC/VDD_VPU/VDD_GPU/VDD_DRAM in i.MX 8M Nano application processor. |
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