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TLE75602-ESH bảng dữ liệu(PDF) 72 Page - Infineon Technologies AG

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Datasheet
72
Rev. 1.0
2017-11-23
TLE75602-ESH
SPIDER+ 12V
Serial Peripheral Interface (SPI)
10.6.3
Register summary
All registers with addresses not mentioned in Table 19 and Table 20 have to be considered as “reserved”.
“Read” operations performed on those registers return the Standard Diagnosis. The column “Default”
indicates the content of the register (8 or 10 bits) after a reset.
PWM_OUT
1001B
00B
8r/w
PWM Generator Output Control
bits PWM_OUT.OUTn
0B
(default) The selected output is not driven by one of
the two PWM Generators
1B
The selected output is connected to a PWM
Generator
PWM_MAP
1001B
01B
8r/w
PWM Generator Output Mapping
bits PWM_MAP.OUTn
0B
(default) The selected output is connected to PWM
Generator 0
1B
The selected output is connected to PWM Generator
1
It is necessary to set the PWM_OUT register to activate the
PWM Generator control for the outputs.
Table 19
Addressable registers (basic functions)
15
14
13-10
9
87
65
43
21
0
Default
r = 0
w = 1
r = 1
w = 0
0000
00
OUT.OUTn
00H
r = 0
w = 1
r = 1
w = 0
0001
00
MAPIN0.OUTn
04H
r = 0
w = 1
r = 1
w = 0
0001
01
MAPIN1.OUTn
08H
0
1
0001
10
TER
(reserved)
INST.INn
00H
r = 0
w = 1
r = 1
w = 0
0010
00
DIAG_IOL.OUTn
00H
0
1
0010
01
DIAG_OSM.OUTn
00H
r = 0
w = 1
r = 1
w = 0
0011
00
HWCR
.ACT
HWCR
.RST
(reserved)
HWCR.PAR
00H
r = 0
w = 1
r = 1
w = 0
0011
01
HWCR_OCL.OUTn
00H
Table 20
Addressable registers (advanced functions)
15
14
13-10
9
87
65
43
21
0
Default
r = 0
w = 1
r = 1
w = 0
0000
01
BIM.OUTn
00H
Table 18
Register addressing space (cont’d)
Register name ADDR0 ADDR1 Size Type Purpose


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