 |
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
|
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
CA5130E bảng dữ liệu(PDF) 6 Page - Intersil Corporation |
|
||||||||||||||||||||||||||||||
CA5130E bảng dữ liệu(HTML) 6 Page - Intersil Corporation |
|
|
6 / 19 page  6 Application Information Circuit Description The input terminals shown in the block diagram of the CA5130 Series CMOS Operational Amplifiers may be operated down to 0.5V below the negative supply rail, and the output can be swung very close to either supply rail in many applications. Consequently, the CA5130 Series circuits are ideal for single supply operation. Three Class A amplifier stages, having the individual gain capability and current consumption shown in the Block Diagram, provide the total gain of the CA5130. A biasing circuit provides two potentials for common use in the first and second stages. Terminal 8 can be used both for phase compensation and to strobe the output stage into quiescence. When Terminal 8 is tied to the negative supply rail (Terminal 4) by mechanical or electrical means, the output potential at Terminal 6 essentially rises to the positive supply rail potential at Terminal 7. This condition of essentially zero current drain in the output stage under the strobed “OFF” condition can only be achieved when the ohmic load resistance presented to the amplifier is very high (e.g., when the amplifier output is used to drive CMOS digital circuits in comparator applications). Input Stages The circuit of the CA5130 is shown in the Schematic Diagram. It consists of a differential input stage using PMOS field-effect transistors (Q6, Q7) working into a mirror pair of bipolar transistors (Q9, Q10) functioning as load resistors together with resistors R3 through R6. The mirror pair transistors also function as a differential-to-single-ended converter to provide base drive to the second stage bipolar transistor (Q11). Offset nulling, when desired, can be effected by connecting a 100,000 Ω potentiometer across Terminals 1 and 5 and the potentiometer slider arm to Terminal 4. Cascode connected PMOS transistors Q2, Q4 are the constant current source for the input stage. The biasing circuit for the constant current source is subsequently described. The small diodes D5 through D8 provide gate oxide protection against high voltage transients, e.g., including static electricity during handling for Q6 and Q7. Second Stage Most of the voltage gain in the CA5130 is provided by the second amplifier stage, consisting of bipolar transistor Q11 and its cascode connected load resistance provided by PMOS transistors Q3 and Q5. The source of bias potentials for these PMOS transistors is subsequently described. Miller-Effect compensation (roll-off) is accomplished by simply connecting a small capacitor between Terminals 1 and 8. A 47pF capacitor provides sufficient compensation for stable unity gain operation in most applications. Bias Source Circuit At total supply voltages, somewhat above 8.3V, resistor R2 and zener diode Z1 serve to establish a voltage of 8.3V across the series connected circuit, consisting of resistor R1, diodes D1 through D4, and PMOS transistor Q1. A tap at the junction of resistor R1 and diode D4 provides a gate bias potential of about 4.5V for PMOS transistors Q4 and Q5 with respect to Terminal 7. A potential of about 2.2V is developed across diode connected PMOS transistor Q1 with respect to Terminal 7 to provide gate bias for PMOS transistors Q2 and Q3. It should be noted that Q1 is “mirror connected” to both Q2 and Q3. Since transistors Q1,Q2,Q3 are designed to be identical, the approximately 200 µA current in Q1 establishes a similar current in Q2 and Q3 as constant current sources for both the first and second amplifier stages, respectively. At total supply voltages somewhat less than 8.3V, zener diode Z1 becomes nonconductive and the potential, developed across series connected R1,D1-D4, and Q1, varies directly with variations in supply voltage. Consequently, the gate bias for Q4, Q5 and Q2, Q3 varies in accordance with supply voltage variations. This variation results in deterioration of the power supply rejection ratio (PSRR) at total supply voltages below 8.3V. Operation at total supply voltages below about 4.5V results in seriously degraded performance. Output Stage The output stage consists of a drain loaded inverting amplifier using CMOS transistors operating in the Class A mode. When operating into very high resistance load, the output can be swung within mV of either supply rail. Because the output stage is a drain loaded amplifier, its gain is dependent upon the load impedance. The transfer characteristics of the output stage for a load returned to the negative supply rail are shown in Figure 15. Typical op amp loads are readily driven by the output stage. Because large signal excursions are nonlinear, requiring feedback for good waveform reproduction, transient delays may be encountered. As a voltage follower, the amplifier can achieve 0.01% accuracy levels, including the negative supply rail. Input Current Variation with Common Mode Input Voltage As shown in the Table of Electrical Specifications, the input current for the CA5130 Series Op Amps is typically 5pA at TA =25 oC when Terminals 2 and 3 are at a common mode potential of +7.5V with respect to negative supply Terminal 4. Figure 24 contains data showing the variation of input current as a function of common mode input voltage at TA =25 oC. This data shows that circuit designers can advantageously exploit these characteristics to design circuits which typically require an input current of less than 1pA, provided the common mode input voltage does not exceed 2V. As previously noted, the input current is essentially the result of the leakage current through the gate protection diodes in the input circuit and, therefore, a function of the applied voltage. Although the finite resistance of the glass terminal-to-case insulator of the metal can package also contributes an increment of leakage current, there are useful compensating factors. Because the gate protection network functions as if it is connected to Terminal 4 potential, and the metal can case of the CA5130 is also internally tied to Terminal 4, input Terminal 3 is essentially “guarded” from spurious leakage currents. CA5130, CA5130A |
Số phần tương tự - CA5130E |
|
Mô tả tương tự - CA5130E |
|
|
|
Link URL |
| Chính sách bảo mật |
| ALLDATASHEET.VN |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
