MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

1

REV 0

6/97

Dual 2-to-4 Decoder/

Demultiplexer

The MC74VHC139 is an advanced high speed CMOS 2–to–4 decoder/

demultiplexer fabricated with silicon gate CMOS technology. It achieves high

speed operation similar to equivalent Bipolar Schottky TTL while maintaining

CMOS low power dissipation.

When the device is enabled (E = low), it can be used for gating or as a data

input for demultiplexing operations. When the enable input is held high, all

four outputs are fixed high, independent of other inputs.

The internal circuit is composed of three stages, including a buffer output

which provides high noise immunity and stable output. The inputs tolerate

voltages up to 7V, allowing the interface of 5V systems to 3V systems.

• High Speed: tPD = 5.0ns (Typ) at VCC = 5V

• Low Power Dissipation: ICC = 4µΑ (Max) at TA = 25°C

• High Noise Immunity: VNIH = VNIL = 28% VCC

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

• Designed for 2V to 5.5V Operating Range

• Low Noise: VOLP = 0.8 V (Max)

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300mA

• ESD Performance: HBM > 2000V; Machine Model > 200V

• Chip Complexity: 100 FETs or 25 Equivalent Gates

LOGIC DIAGRAM

A0a

A1a

Ea

A0b

A1b

1

Eb

Y0a

Y1a

Y2a

Y3a

Y0b

Y1b

Y2b

Y3b

ACTIVE–LOW

OUTPUTS

ADDRESS

INPUTS

ACTIVE–LOW

OUTPUTS

3

2

ADDRESS

INPUTS

13

14

15

4

5

6

7

12

11

10

9

MC74VHC139

D SUFFIX

16–LEAD SOIC PACKAGE

CASE 751B–05

DT SUFFIX

16–LEAD TSSOP PACKAGE

CASE 948F–01

ORDERING INFORMATION

MC74VHCXXXD

MC74VHCXXXDT

MC74VHCXXXM

SOIC

TSSOP

SOIC EIAJ

M SUFFIX

16–LEAD SOIC EIAJ PACKAGE

CASE 966–01

FUNCTION TABLE

PIN ASSIGNMENT

Inputs

Outputs

E

A1

A0

Y0

Y1 Y2

Y3

HX

X

H

H

H

H

LL

L

L

H

H

H

LL

H

H

L

H

H

LH

L

H

H

L

H

LH

H

H

H

H

L

13

14

15

16

9

10

11

12

5

4

3

2

1

8

7

6

Ea

A1a

A0a

GND

A1b

A0b

Eb

VCC

Y0a

Y1a

Y2a

Y3a

Y0b

Y1b

Y2b

Y3b