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MC74VHC125 bảng dữ liệu(PDF) 1 Page - ON Semiconductor |
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MC74VHC125 bảng dữ liệu(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2000 April, 2000 – Rev. 2 1 Publication Order Number: MC74VHC125/D MC74VHC125 Quad Bus Buffer with 3–State Control Inputs The MC74VHC125 is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC125 requires the 3–state control input (OE) to be set High to place the output into the high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. • High Speed: tPD = 3.8ns (Typ) at VCC = 5V • Low Power Dissipation: ICC = 4µA (Max) at TA = 25°C • High Noise Immunity: VNIH = VNIL = 28% VCC • Power Down Protection Provided on Inputs • Balanced Propagation Delays • Designed for 2V to 5.5V Operating Range • Low Noise: VOLP = 0.8V (Max) • Pin and Function Compatible with Other Standard Logic Families • Latchup Performance Exceeds 300mA • ESD Performance: HBM > 2000V; Machine Model > 200V • Chip Complexity: 72 FETs or 18 Equivalent Gates LOGIC DIAGRAM Active–Low Output Enables Y1 Y2 Y4 3 6 8 11 13 12 10 9 4 5 1 2 A1 OE1 A2 OE2 A3 OE3 A4 OE4 Y3 FUNCTION TABLE VHC125 Inputs Output AOE Y HL H LL L XH Z 14–LEAD SOIC D SUFFIX CASE 751A http://onsemi.com 14–LEAD TSSOP DT SUFFIX CASE 948G PIN CONNECTION AND MARKING DIAGRAM (Top View) Device Package Shipping ORDERING INFORMATION MC74VHC125D SOIC 55 Units/Rail MC74VHC125DT TSSOP 96 Units/Rail 14–LEAD SOIC EIAJ M SUFFIX CASE 965 MC74VHC125M SOIC EIAJ 50 Units/Rail For detailed package marking information, see the Marking Diagram section on page 5 of this data sheet. 11 12 13 14 8 9 10 5 4 3 2 1 7 6 OE3 Y4 A4 OE4 VCC Y3 A3 OE2 Y1 A1 OE1 GND Y2 A2 |
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