công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

TLIN1028-Q1 bảng dữ liệu(PDF) 7 Page - Texas Instruments

tên linh kiện TLIN1028-Q1
Giải thích chi tiết về linh kiện  TLIN1028-Q1 Automotive Local Interconnect Network (LIN) Transceiver with Integrated Voltage Regulator
Download  35 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  TI1 [Texas Instruments]
Trang chủ  http://www.ti.com
Logo TI1 - Texas Instruments

TLIN1028-Q1 bảng dữ liệu(HTML) 7 Page - Texas Instruments

Back Button TLIN1028-Q1_V01 Datasheet HTML 3Page - Texas Instruments TLIN1028-Q1_V01 Datasheet HTML 4Page - Texas Instruments TLIN1028-Q1_V01 Datasheet HTML 5Page - Texas Instruments TLIN1028-Q1_V01 Datasheet HTML 6Page - Texas Instruments TLIN1028-Q1_V01 Datasheet HTML 7Page - Texas Instruments TLIN1028-Q1_V01 Datasheet HTML 8Page - Texas Instruments TLIN1028-Q1_V01 Datasheet HTML 9Page - Texas Instruments TLIN1028-Q1_V01 Datasheet HTML 10Page - Texas Instruments TLIN1028-Q1_V01 Datasheet HTML 11Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 35 page
background image
7
TLIN1028-Q1
www.ti.com
SLLSEX4 – AUGUST 2019
Product Folder Links: TLIN1028-Q1
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
ELECTRICAL CHARACTERISTICS (continued)
parameters valid over –40
℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I BUS_PAS_dom
Receiver leakage current, dominant (ISO/DIS
17987 Param 13)
VLIN = 0 V, VSUP = 12 V Driver off/recessive,
RMEAS = 499 Ω; Figure 7
–1
mA
I BUS_PAS_rec1
Receiver leakage current, recessive (ISO/DIS
17987 Param 14)
VLIN ≥ VSUP, 5.5 V ≤ VSUP ≤ 36 V Driver off,
RMEAS = 1 kΩ; Figure 8
20
µA
I BUS_PAS_rec2
Receiver leakage current, recessive (ISO/DIS
17987 Param 14)
VLIN = VSUP, Driver off, RMEAS = 1 kΩ;
Figure 8
–8
8
µA
I BUS_NO_GND
Leakage current, loss of ground (ISO/DIS 17987
Param 15)
GND = VSUP, VSUP = 12 V, 0 V ≤ VLIN ≤ 28
V, RMEAS = 1 kΩ; Figure 9
–1
1
mA
IBUS_NO_BAT
Leakage current, loss of supply (ISO/DIS 17987
Param 16)
0 V
≤ VLIN ≤ 28 V, VSUP = GND, RMEAS = 10
k
Ω; Figure 10
8
µA
VBUSdom
Low level input voltage (ISO/DIS 17987 Param
17)
LIN dominant (including LIN dominant for
wake up); Figure 3, Figure 4
0.4
VSUP
VBUSrec
High level input voltage (ISO/DIS 17987 Param
18)
LIN recessive; Figure 3, Figure 4
0.6
VSUP
VBUS_CNT
Receiver center threshold (ISO/DIS 17987 Param
19)
VBUS_CNT = (VIL + VIH)/2; Figure 3, Figure 4
0.475
0.5
0.525
VSUP
VHYS
Hysteresis voltage (ISO/DIS 17987 Param 20)
VHYS = (VIL - VIH); Figure 3, Figure 4
0.175
VSUP
VSERIAL_DIODE
Serial diode LIN term pull-up path (ISO/DIS
17987 Param 21)
By design and characterization
0.4
0.7
1.0
V
RSLAVE
Pull-up resistor to VSUP (ISO/DIS 17987 Param
26)
Normal and Standby modes
20
45
60
k
IRSLEEP
Pull-up current source to VSUP
Sleep mode, VSUP = 12 V, LIN = GND
–20
–2
µA
CLIN,PIN
Capacitance of the LIN pin
55
pF
EN INPUT TERMINAL
VIH
High level input voltage
2
5.5
V
VIL
Low level input voltage
–0.3
0.8
V
VHYS
Hysteresis voltage
By design and characterization
30
500
mV
IIL
Low level input current
EN = Low
–5
0
5
µA
REN
Internal pull-down resistor
125
350
800
k
nRST TERMINAL (OPEN DRAIN OUTPUT)
ILKG
Leakage current, high-level
LIN = VSUP, nRST = VCC
–5
5
µA
VOL
Low-level output voltage
Based upon external pull up to VCC
0.2
VCC
IOL
Low-level output current, open drain
LIN = 0 V, nRST = 0.4 V
1.5
mA
DUTY CYCLE CHARACTERISTICS
D112V
Duty Cycle 1 (ISO/DIS 17987 Param 27)
THREC(MAX) = 0.744 x VSUP,
THDOM(MAX) = 0.581 x VSUP,
VSUP = 5.5 V to 18 V, tBIT = 50 µs (20 kbps),
D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 11,
Figure 12)
0.396
D212V
Duty Cycle 2 (ISO/DIS 17987 Param 28)
THREC(MIN) = 0.422 x VSUP,
THDOM(MIN) = 0.284 x VSUP, VSUP = 5.5 V to
18 V,
tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x
tBIT) (See Figure 11, Figure 12)
0.581
D312V
Duty Cycle 3 (ISO/DIS 17987 Param 29)
THREC(MAX) = 0.778 x VSUP, THDOM(MAX) =
0.616 x VSUP,
VSUP = 5.5 V to 18 V, tBIT = 96 µs (10.4
kbps),
D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 11,
Figure 12)
0.417
D412V
Duty Cycle 4 (ISO/DIS 17987 Param 30)
THREC(MIN) = 0.389 x VSUP,
THDOM(MIN) = 0.251 x VSUP,
VSUP = 5.5 V to 18 V, tBIT = 96 µs (10.4
kbps),
D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 11,
Figure 12)
0.59


Số phần tương tự - TLIN1028-Q1_V01

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
logo
Texas Instruments
TLIN1028-Q1 TI1-TLIN1028-Q1 Datasheet
1Mb / 38P
[Old version datasheet]   TLIN1028-Q1 Automotive Local Interconnect Network (LIN) Transceiver with Integrated Voltage Regulator
More results

Mô tả tương tự - TLIN1028-Q1_V01

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
logo
Texas Instruments
TLIN1028-Q1 TI1-TLIN1028-Q1 Datasheet
1Mb / 38P
[Old version datasheet]   TLIN1028-Q1 Automotive Local Interconnect Network (LIN) Transceiver with Integrated Voltage Regulator
TLIN1441-Q1 TI1-TLIN1441-Q1 Datasheet
1Mb / 55P
[Old version datasheet]   Automotive Local Interconnect Network (LIN) Transceiver with Integrated Voltage Regulator and Watchdog
TLIN2441-Q1 TI1-TLIN2441-Q1 Datasheet
1Mb / 55P
[Old version datasheet]   Automotive Local Interconnect Network (LIN) Transceiver with Integrated Voltage Regulator and Watchdog
TLIN1027-Q1 TI1-TLIN1027-Q1 Datasheet
1Mb / 32P
[Old version datasheet]   TLIN1027-Q1 Local Interconnect Network (LIN) Transceiver
TLIN1021-Q1 TI1-TLIN1021-Q1 Datasheet
1Mb / 41P
[Old version datasheet]   TLIN1021-Q1 Local Interconnect Network (LIN) Transceiver with Local Wake and Inhibit
TLIN2027-Q1 TI1-TLIN2027-Q1 Datasheet
1Mb / 31P
[Old version datasheet]   TLIN2027-Q1 Fault Protected Local Interconnect Network (LIN) Transceiver
TLIN1039-Q1 TI-TLIN1039-Q1 Datasheet
2Mb / 38P
[Old version datasheet]   TLIN1039-Q1 Local Interconnect Network (LIN) Transceiver with Dominant State Timeout
SLLSFH7 ??AUGUST 2021
TLIN1022A-Q1 TI-TLIN1022A-Q1 Datasheet
2Mb / 45P
[Old version datasheet]   TLIN1022A-Q1 Dual Local Interconnect Network (LIN) Transceiver with Dominant State Timeout
TLIN2024A-Q1 TI-TLIN2024A-Q1 Datasheet
2Mb / 39P
[Old version datasheet]   TLIN2024A-Q1 Quad Local Interconnect Network (LIN) Transceiver with Dominant State Timeout
JUNE 2022
TLIN2022A-Q1 TI-TLIN2022A-Q1 Datasheet
2Mb / 45P
[Old version datasheet]   TLIN2022A-Q1 Dual Local Interconnect Network (LIN) Transceiver with Dominant State Timeout
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35


bảng dữ liệu tải về

Go To PDF Page


Link URL




Chính sách bảo mật
ALLDATASHEET.VN
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com