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MSP430FR6007 bảng dữ liệu(PDF) 93 Page - Texas Instruments |
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MSP430FR6007 bảng dữ liệu(HTML) 93 Page - Texas Instruments |
93 / 179 page 93 MSP430FR6007, MSP430FR6005 www.ti.com SLASEV3 – MARCH 2020 Submit Documentation Feedback Product Folder Links: MSP430FR6007 MSP430FR6005 Detailed Description Copyright © 2020, Texas Instruments Incorporated 6.14 Input/Output Diagrams 6.14.1 Port Function Select Registers (PySEL1 , PySEL0) Port pins are multiplexed with peripheral module functions as described in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide. The functions of each port pin are controlled by its port function select registers, PySEL1 and PySEL0, where y = port number. The bits in the registers are mapped to the pins in the port. The primary module function, secondary module function, and tertiary module function of the pins are determined by the configuration of the PySEL1.x and PySEL0.x bits (see Table 6-24). For example, P1SEL1.0 and P1SEL0.0 determine the primary module function, secondary module function, and tertiary module function of the P1.0 pin, which is in port 1. The module functions may also require the PxDIR bits to be configured according to the direction needed for the module function. Table 6-24. I/O Function Selection I/O FUNCTIONS PySEL1.x PySEL0.x General-purpose I/O is selected 0 0 Primary module function is selected 0 1 Secondary module function is selected 1 0 Tertiary module function is selected 1 1 See the port pin function tables in the following sections for the configurations of the function and direction for each pin. |
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Mô tả tương tự - MSP430FR6007 |
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