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ET1100 bảng dữ liệu(PDF) 96 Page - Beckhoff Automation GmbH & Co. KG |
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ET1100 bảng dữ liệu(HTML) 96 Page - Beckhoff Automation GmbH & Co. KG |
96 / 124 page PDI Description III-82 Slave Controller – ET1100 Hardware Description BHE1 CS BHE WR RD DATA BUSY ADR1 ADR tWR_active tWR_to_BUSY tCS_delay tWR_delay tADR_BHE_DATA_hold DATA1 tADR_BHE_DATA_setup twrite_int tCS_to_BUSY tCS_to_BUSY tCS_to_BUSY Internal state Writing ADR1 BHE2 ADR2 tWR_active tWR_to_BUSY tBUSY_to_WR tCS_delay tADR_BHE_DATA_hold DATA2 tADR_BHE_DATA_setup tread ADR3 BHE3 tCS_to_BUSY tCS_to_BUSY Idle Writing ADR2 Reading ADR3 DATA3 Idle Idle twrite twrite_int tWR_to_RD tread_int tBUSY_to_DATA_valid Coll. tcoll Figure 37: Sequence of two write accesses and a read access Note: The first write access to ADR1 is performed after the first rising edge of WR. After that, the ESC is internally busy writing to ADR1. After CS is de-asserted, BUSY is not driven any more, nevertheless, the ESC is still writing to ADR1. Hence, the second write access to ADR2 is delayed because the write access to ADR1 has to be completed first. So, the second rising edge of WR must not occur before BUSY is gone. After the second rising edge of WR, the ESC is busy writing to ADR2. This is reflected with the BUSY signal as long as CS is asserted. The third access in this example is a read access. The ESC is still busy writing to ADR2 while the falling edge of RD occurs. In this case, the write access to ADR2 is finished first, and afterwards, the read access to ADR3 is performed. The ESC signals BUSY during both write and read access. |
Số phần tương tự - ET1100 |
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Mô tả tương tự - ET1100 |
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