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MSP430F5507 bảng dữ liệu(PDF) 7 Page - Texas Instruments |
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MSP430F5507 bảng dữ liệu(HTML) 7 Page - Texas Instruments |
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7 / 125 page  7 MSP430F5510, MSP430F5509, MSP430F5508 MSP430F5507, MSP430F5506, MSP430F5505, MSP430F5504 MSP430F5503, MSP430F5502, MSP430F5501, MSP430F5500 www.ti.com SLAS645L – JULY 2009 – REVISED MAY 2020 Submit Documentation Feedback Product Folder Links: MSP430F5510 MSP430F5509 MSP430F5508 MSP430F5507 MSP430F5506 MSP430F5505 MSP430F5504 MSP430F5503 MSP430F5502 MSP430F5501 MSP430F5500 Device Comparison Copyright © 2009–2020, Texas Instruments Incorporated (1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com. (2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging. (3) The additional 2KB USB SRAM that is listed can be used as general-purpose SRAM when USB is not in use. (4) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively. (5) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively. (6) Two USCIs are available; however, pinned out functions are limited to what the user configures on port 4 with the port mapping controller (see Section 6.9.2). It may not be possible to bring out all functions simultaneously. 3 Device Comparison Table 3-1 summarizes the available family members. Table 3-1. Device Comparison(1)(2) DEVICE PROGRAM MEMORY (KB) SRAM (KB)(3) Timer_A(4) Timer_B(5) USCI ADC10_A (CH) Comp_B (CH) I/Os PACKAGE CHANNEL A: UART, LIN, IrDA, SPI CHANNEL B: SPI, I2C MSP430F5510 32 4 + 2 5, 3, 3 7 2 2 10 ext, 2 int 8 47 64 RGC, 80 ZXH, 80 ZQE 2(6) 2(6) 6 ext, 2 int 4 31 48 PT, 48 RGZ MSP430F5509 24 4 + 2 5, 3, 3 7 2 2 10 ext, 2 int 8 47 64 RGC, 80 ZXH, 80 ZQE 2(6) 2(6) 6 ext, 2 int 4 31 48 PT, 48 RGZ, MSP430F5508 16 4 + 2 5, 3, 3 7 2 2 10 ext, 2 int 8 47 64 RGC, 80 ZXH, 80 ZQE 2(6) 2(6) 6 ext, 2 int 4 31 48 PT, 48 RGZ, MSP430F5507 32 4 + 2 5, 3, 3 7 1 1 6 ext, 2 int – 31 48 RGZ MSP430F5506 24 4 + 2 5, 3, 3 7 1 1 6 ext, 2 int – 31 48 RGZ MSP430F5505 16 4 + 2 5, 3, 3 7 1 1 6 ext, 2 int – 31 48 RGZ MSP430F5504 8 4 + 2 5, 3, 3 7 1 1 6 ext, 2 int – 31 48 PT, 48 RGZ MSP430F5503 32 4 + 2 5, 3, 3 7 1 1 – 4 31 48 RGZ MSP430F5502 24 4 + 2 5, 3, 3 7 1 1 – 4 31 48 RGZ MSP430F5501 16 4 + 2 5, 3, 3 7 1 1 – 4 31 48 RGZ MSP430F5500 8 4 + 2 5, 3, 3 7 1 1 – 4 31 48 RGZ |
Số phần tương tự - MSP430F5507 |
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Mô tả tương tự - MSP430F5507 |
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