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MSP430F5310 bảng dữ liệu(PDF) 74 Page - Texas Instruments |
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MSP430F5310 bảng dữ liệu(HTML) 74 Page - Texas Instruments |
74 / 109 page P4.0/P4MAP0 P4.1/P4MAP1 P4.2/P4MAP2 P4.3/P4MAP3 P4.4/P4MAP4 P4.5/P4MAP5 P4.6/P4MAP6 P4.7/P4MAP7 Direction 0: Input 1: Output P4SEL.x 1 0 P4DIR.x P4IN.x EN To Port Mapping Control 1 0 From Port Mapping Control P4OUT.x 1 0 DV SS DV CC P4REN.x Pad Logic 1 P4DS.x 0: Low drive 1: High drive D From Port Mapping Control 74 MSP430F5310, MSP430F5309, MSP430F5308, MSP430F5304 SLAS677G – SEPTEMBER 2010 – REVISED MAY 2020 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304 Detailed Description Copyright © 2010–2020, Texas Instruments Incorporated (1) The direction of some mapped secondary functions are controlled directly by the module. See Table 6-6 for specific direction control information of mapped secondary functions. 6.11.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger Figure 6-5 shows the port diagram. Table 6-46 summarizes the selection of the pin functions. Figure 6-5. Port P4 (P4.0 to P4.7) Diagram Table 6-46. Port P4 (P4.0 to P4.7) Pin Functions PIN NAME (P4.x) x FUNCTION CONTROL BITS OR SIGNALS P4DIR.x(1) P4SEL.x P4MAPx P4.0/P4MAP0 0 P4.0 (I/O) I: 0; O: 1 0 X Mapped secondary digital function X 1 ≤ 30 P4.1/P4MAP1 1 P4.1 (I/O) I: 0; O: 1 0 X Mapped secondary digital function X 1 ≤ 30 P4.2/P4MAP2 2 P4.2 (I/O) I: 0; O: 1 0 X Mapped secondary digital function X 1 ≤ 30 P4.3/P4MAP3 3 P4.3 (I/O) I: 0; O: 1 0 X Mapped secondary digital function X 1 ≤ 30 P4.4/P4MAP4 4 P4.4 (I/O) I: 0; O: 1 0 X Mapped secondary digital function X 1 ≤ 30 P4.5/P4MAP5 5 P4.5 (I/O) I: 0; O: 1 0 X Mapped secondary digital function X 1 ≤ 30 P4.6/P4MAP6 6 P4.6 (I/O) I: 0; O: 1 0 X Mapped secondary digital function X 1 ≤ 30 P4.7/P4MAP7 7 P4.7 (I/O) I: 0; O: 1 0 X Mapped secondary digital function X 1 ≤ 30 |
Số phần tương tự - MSP430F5310_V01 |
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Mô tả tương tự - MSP430F5310_V01 |
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