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MSP430F5310 bảng dữ liệu(PDF) 52 Page - Texas Instruments

tên linh kiện MSP430F5310
Giải thích chi tiết về linh kiện  MSP430F5310, MSP430F530x Mixed-Signal Microcontrollers
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MSP430F5310, MSP430F5309, MSP430F5308, MSP430F5304
SLAS677G – SEPTEMBER 2010 – REVISED MAY 2020
www.ti.com
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Product Folder Links: MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304
Detailed Description
Copyright © 2010–2020, Texas Instruments Incorporated
6.9.9
DMA Controller (Link to User's Guide)
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC10_A conversion
register to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral. Table 6-9 lists the triggers for DMA transfers.
(1)
If a reserved trigger source is selected, no trigger is generated.
(2)
Only on devices with ADC. Reserved on devices without ADC.
Table 6-9. DMA Trigger Assignments (1)
TRIGGER
CHANNEL
0
1
2
0
DMAREQ
DMAREQ
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR0 CCIFG
TA0CCR0 CCIFG
2
TA0CCR2 CCIFG
TA0CCR2 CCIFG
TA0CCR2 CCIFG
3
TA1CCR0 CCIFG
TA1CCR0 CCIFG
TA1CCR0 CCIFG
4
TA1CCR2 CCIFG
TA1CCR2 CCIFG
TA1CCR2 CCIFG
5
TA2CCR0 CCIFG
TA2CCR0 CCIFG
TA2CCR0 CCIFG
6
TA2CCR2 CCIFG
TA2CCR2 CCIFG
TA2CCR2 CCIFG
7
TB0CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR0 CCIFG
8
TB0CCR2 CCIFG
TB0CCR2 CCIFG
TB0CCR2 CCIFG
9
Reserved
Reserved
Reserved
10
Reserved
Reserved
Reserved
11
Reserved
Reserved
Reserved
12
Reserved
Reserved
Reserved
13
Reserved
Reserved
Reserved
14
Reserved
Reserved
Reserved
15
Reserved
Reserved
Reserved
16
UCA0RXIFG
UCA0RXIFG
UCA0RXIFG
17
UCA0TXIFG
UCA0TXIFG
UCA0TXIFG
18
UCB0RXIFG
UCB0RXIFG
UCB0RXIFG
19
UCB0TXIFG
UCB0TXIFG
UCB0TXIFG
20
UCA1RXIFG
UCA1RXIFG
UCA1RXIFG
21
UCA1TXIFG
UCA1TXIFG
UCA1TXIFG
22
UCB1RXIFG
UCB1RXIFG
UCB1RXIFG
23
UCB1TXIFG
UCB1TXIFG
UCB1TXIFG
24
ADC10IFG0 (2)
ADC10IFG0 (2)
ADC10IFG0 (2)
25
Reserved
Reserved
Reserved
26
Reserved
Reserved
Reserved
27
reserved
reserved
reserved
28
reserved
reserved
reserved
29
MPY ready
MPY ready
MPY ready
30
DMA2IFG
DMA0IFG
DMA1IFG
31
DMAE0
DMAE0
DMAE0


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