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MSP430F5310 bảng dữ liệu(PDF) 41 Page - Texas Instruments

tên linh kiện MSP430F5310
Giải thích chi tiết về linh kiện  MSP430F5310, MSP430F530x Mixed-Signal Microcontrollers
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MSP430F5310, MSP430F5309, MSP430F5308, MSP430F5304
www.ti.com
SLAS677G – SEPTEMBER 2010 – REVISED MAY 2020
Submit Documentation Feedback
Product Folder Links: MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304
Specifications
Copyright © 2010–2020, Texas Instruments Incorporated
(1)
The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
(2)
These values are hardwired into the state machine of the flash controller.
5.42 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TJ
MIN
TYP
MAX
UNIT
DVCC(PGM/ERASE)
Program or erase supply voltage
1.8
3.6
V
tREADMARGIN
Read access time during margin mode
200
ns
IPGM
Supply current from DVCC during program
3
5
mA
IERASE
Supply current from DVCC during erase
2
6.5
mA
IMERASE, IBANK
Supply current from DVCC during mass erase or bank erase
2
6.5
mA
tCPT
Cumulative program time(1)
16
ms
Program and erase endurance
104
105
cycles
tRetention
Data retention duration
25°C
100
years
tWord
Word or byte program time(2)
64
85
µs
tBlock, 0
Block program time for first byte or word(2)
49
65
µs
tBlock, 1–(N–1)
Block program time for each additional byte or word, except for last byte
or word(2)
37
49
µs
tBlock, N
Block program time for last byte or word(2)
55
73
µs
tErase
Erase time for segment, mass erase, and bank erase when available(2)
23
32
ms
(1)
Tools that access the Spy-Bi-Wire and BSL interfaces must wait for the tSBW,En time after the first transition of the TEST/SBWTCK pin
(low to high), before the second transition of the pin (high to low) during the entry sequence.
(2)
fTCK may be restricted to meet the timing requirements of the module selected.
5.43 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.2 V, 3 V
0.025
15
µs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1)
2.2 V, 3 V
1
µs
tSBW,Rst
Spy-Bi-Wire return to normal operation time
15
100
µs
fTCK
TCK input frequency, 4-wire JTAG(2)
2.2 V
0
5
MHz
3 V
0
10
MHz
Rinternal
Internal pulldown resistance on TEST
2.2 V, 3 V
45
60
80
k


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