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MSP430F5310 bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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MSP430F5310 bảng dữ liệu(HTML) 4 Page - Texas Instruments |
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4 / 109 page  Unified Clock System 8KB Flash 6KB RAM MCLK ACLK SMCLK CPUXV2 and Working Registers EEM (S:3+1) XIN XOUT JTAG, SBW Interface DMA 3 Channel XT2IN XT2OUT Power Management LDO SVM/SVS Brownout SYS Watchdog Port Map Control (P4) PU Port LDO MPY32 TA0 Timer_A 5 CC Registers TA1 Timer_A 3 CC Registers TB0 Timer_B 7 CC Registers RTC_A CRC16 USCI1 A1: UART, IrDA, SPI B1: SPI, I2C DVCC DVSS AVCC AVSS PU.0, PU.1 RST/NMI TA2 Timer_A 3 CC Registers REF VCORE MAB MDB ADC10_A 200 KSPS 8 Channels (6 int, 2 ext) Window Comparator 10 Bit I/O Ports P1, P2 1×8 I/Os 1 Interrupt, Wakeup PA 1×9 I/Os ×1 I/Os PA PB PC I/O Ports P4 1 PB 1×8 I/Os ×8 I/Os I/O Ports P5, P6 1×6 I/Os 1 PC 1×10 I/Os ×4 I/Os P1.x P2.x P3.x P4.x P5.x P6.x Copyright © 2016, Texas Instruments Incorporated Unified Clock System 32KB 24KB 16KB Flash 6KB RAM MCLK ACLK SMCLK CPUXV2 and Working Registers EEM (S:3+1) XIN XOUT JTAG, SBW Interface DMA 3 Channel XT2IN XT2OUT Power Management LDO SVM/SVS Brownout SYS Watchdog Port Map Control (P4) PU Port LDO MPY32 TA0 Timer_A 5 CC Registers TA1 Timer_A 3 CC Registers TB0 Timer_B 7 CC Registers RTC_A CRC16 USCI0,1 Ax: UART, IrDA, SPI Bx: SPI, I2C COMP_B DVCC DVSS AVCC AVSS PU.0, PU.1 RST/NMI TA2 Timer_A 3 CC Registers REF VCORE MAB MDB ADC10_A 200 KSPS 8 Channels (6 ext, 2 int) Window Comparator 10 Bit I/O Ports P1, P2 1×8 I/Os 1 Interrupt, Wakeup PA 1×9 I/Os ×1 I/Os PA PB PC I/O Ports P4 1 PB 1×8 I/Os ×8 I/Os I/O Ports P5, P6 1×6 I/Os 1 PC 1×10 I/Os ×4 I/Os P1.x P2.x P3.x P4.x P5.x P6.x Copyright © 2016, Texas Instruments Incorporated 4 MSP430F5310, MSP430F5309, MSP430F5308, MSP430F5304 SLAS677G – SEPTEMBER 2010 – REVISED MAY 2020 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430F5310 MSP430F5309 MSP430F5308 MSP430F5304 Device Overview Copyright © 2010–2020, Texas Instruments Incorporated NOTE: See Table 3-1 for limitations on the simultaneous availability of USCI module signals. Figure 1-2. Functional Block Diagram – RGZ or PT Package – MSP430F5310, MSP430F5309, MSP430F5308 Figure 1-3. Functional Block Diagram – RGZ or PT Package – MSP430F5304 |
Số phần tương tự - MSP430F5310_V01 |
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Mô tả tương tự - MSP430F5310_V01 |
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