công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TP3057V-X bảng dữ liệu(PDF) 4 Page - National Semiconductor (TI) |
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TP3057V-X bảng dữ liệu(HTML) 4 Page - National Semiconductor (TI) |
4 / 16 page Functional Description (Continued) LONG FRAME SYNC OPERATION To use the long frame mode, both the frame sync pulses, FS X and FSR, must be three or more bit clock periods long, with timing relationships specified in Figure 3. Based on the transmit frame sync, FS X, the COMBO will sense whether short or long frame sync pulses are being used. For 64 kHz operation, the frame sync pulse must be kept low for a minimum of 160 ns. The D X TRI-STATE output buffer is enabled with the rising edge of FS X or the rising edge of BCLK X, whichever comes later, and the first bit clocked out is the sign bit. The following seven BCLK X rising edges clock out the remaining seven bits. The D X output is disabled by the falling BCLK X edge following the eighth rising edge, or by FS X going low, whichever comes later. A rising edge on the receive frame sync pulse, FS R, will cause the PCM data at D R to be latched in on the next eight falling edges of BCLKR (BCLK X in synchronous mode). All four devices may utilize the long frame sync pulse in synchronous or asynchronous mode. In applications where the LSB bit is used for signalling, with FS R two bit clock periods long, the decoder will interpret the lost LSB as “1⁄2” to minimize noise and distortion. TRANSMIT SECTION The transmit section input is an operational amplifier with provision for gain adjustment using two external resistors, see Figure 4. The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz. The output of this filter directly drives the encoder sample-and-hold circuit. The A/D is of companding type according to µ-law (TP3054) or A-law (TP3057) coding conventions. A precision voltage reference is trimmed in manufacturing to provide an input overload (t MAX) of nominally 2.5V peak (see table of Transmission Characteristics). The FS X frame sync pulse controls the sampling of the filter output, and then the successive- approximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted out through D X at the next FS X pulse. The total encoding delay will be approximately 165 µs (due to the transmit filter) plus 125 µs (due to encod- ing delay), which totals 290 µs. Any offset voltage due to the filters or comparator is cancelled by sign bit integration. RECEIVE SECTION The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz. The decoder is A-law (TP3057) or µ-law (TP3054) and the 5th order low pass filter corrects for the sin x/x attenuation due to the 8 kHz sample/hold. The filter is then followed by a 2nd order RC active post-filter/power amplifier capable of driving a 600 Ω load to a level of 7.2 dBm. The receive section is unity-gain. Upon the occurrence of FS R, the data at the DR input is clocked in on the falling edge of the next eight BCLK R (BCLKX) periods. At the end of the decoder time slot, the decoding cycle begins, and 10 µs later the decoder DAC output is updated. The total decoder delay is ∼10 µs (decoder update) plus 110 µs (filter delay) plus 62.5 µs (1⁄2 frame), which gives approximately 180 µs. www.national.com 4 |
Số phần tương tự - TP3057V-X |
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Mô tả tương tự - TP3057V-X |
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