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MC14526BF bảng dữ liệu(PDF) 4 Page - ON Semiconductor |
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MC14526BF bảng dữ liệu(HTML) 4 Page - ON Semiconductor |
4 / 12 page MC14526B http://onsemi.com 4 SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C) Characteristic Symbol VDD Min Typ (8.) Max Unit Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL (Figures 4, 5) 5.0 10 15 — — — 100 50 40 200 100 80 ns Propagation Delay Time (Inhibit Used as Negative Edge Clock) Clock or Inhibit to Q tPLH, tPHL = (1.7 ns/pF) CL + 465 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 135 ns tPLH, tPHL (Figures 4, 5, 6) 5.0 10 15 — — — 550 225 160 1100 450 320 ns Clock or Inhibit to “0” tPLH, tPHL = (1.7 ns/pF) CL + 155 ns tPLH, tPHL = (0.66 ns/pF) CL + 87 ns tPLH, tPHL = (0.5 ns/pF) CL + 65 ns 5.0 10 15 — — — 240 130 100 480 260 200 Propagation Delay Time Pn to Q tPLH, tPHL (Figures 4, 7) 5.0 10 15 — — — 260 120 100 520 240 200 ns Propagation Delay Time Reset to Q tPHL (Figure 8) 5.0 10 15 — — — 250 110 80 500 220 160 ns Propagation Delay Time Preset Enable to “0” tPHL, tPLH (Figures 4, 9) 5.0 10 15 — — — 220 100 80 440 200 160 ns Clock or Inhibit Pulse Width tw (Figures 5, 6) 5.0 10 15 250 100 80 125 50 40 — — — ns Clock Pulse Frequency (with PE = low) fmax (Figures 4, 5, 6) 5.0 10 15 — — — 2.0 5.0 6.6 1.5 3.0 4.0 MHz Clock or Inhibit Rise and Fall Time tr, tf (Figures 5, 6) 5.0 10 15 — — — — — — 15 5 4 µs Setup Time Pn to Preset Enable tsu (Figure 10) 5.0 10 15 90 50 40 40 15 10 — — — ns Hold Time Preset Enable to Pn th (Figure 10) 5.0 10 15 30 30 30 – 15 – 5 0 — — — ns Preset Enable Pulse Width tw (Figure 10) 5.0 10 15 250 100 80 125 50 40 — — — ns Reset Pulse Width tw (Figure 8) 5.0 10 15 350 250 200 175 125 100 — — — ns Reset Removal Time trem (Figure 8) 5.0 10 15 10 20 30 – 110 – 30 – 20 — — — ns 7. The formulas given are for the typical characteristics only at 25 _C. 8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. |
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