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MC14526BDW bảng dữ liệu(PDF) 7 Page - ON Semiconductor |
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MC14526BDW bảng dữ liệu(HTML) 7 Page - ON Semiconductor |
7 / 12 page MC14526B http://onsemi.com 7 PIN DESCRIPTIONS Preset Enable (Pin 3) — If Reset is low, a high level on the Preset Enable input asynchronously loads the counter with the programmed values on P0, P1, P2, and P3. Inhibit (Pin 4) — A high level on the Inhibit input pre– vents the Clock from decrementing the counter. With Clock (pin 6) held high, Inhibit may be used as a negative edge clock input. Clock (Pin 6) — The counter decrements by one for each rising edge of Clock. See the Function Table for level requirements on the other inputs. Reset (Pin 10) — A high level on Reset asynchronously forces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback is high, causes the “0” output to go high. “0” (Pin 12) — The “0” (Zero) output issues a pulse one clock period wide when the counter reaches terminal count (Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high and Preset Enable is low. When presetting the counter to a value other than all zeroes, the “0” output is valid after the rising edge of Preset Enable (when Cascade Feedback is high). See the Function Table. Cascade Feedback (Pin 13) — If the Cascade Feedback input is high, a high level is generated at the “0” output when the count is all zeroes. If Cascade Feedback is low, the “0” output depends on the Preset Enable input level. See the Function Table. P0, P1, P2, P3 (Pins 5, 11, 14, 2) — These are the preset data inputs. P0 is the LSB. Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) — These are the synchronous counter outputs. Q0 is the LSB. VSS (Pin 8) — The most negative power supply potential. This pin is usually ground. VDD (Pin 16) — The most positive power supply potential. VDD may range from 3 to 18 V with respect to VSS. STATE DIAGRAM MC14526B 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 |
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