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Giải thích chi tiết về linh kiện  Hex Contact Bounce Eliminator
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© Semiconductor Components Industries, LLC, 2000
May, 2000 – Rev. 4
1
Publication Order Number:
MC14490/D
MC14490
Hex Contact Bounce
Eliminator
The MC14490 is constructed with complementary MOS
enhancement mode devices, and is used for the elimination of
extraneous level changes that result when interfacing with mechanical
contacts. The digital contact bounce eliminator circuit takes an input
signal from a bouncing contact and generates a clean digital signal
four clock periods after the input has stabilized. The bounce eliminator
circuit will remove bounce on both the “make” and the “break” of a
contact closure. The clock for operation of the MC14490 is derived
from an internal R–C oscillator which requires only an external
capacitor to adjust for the desired operating frequency (bounce delay).
The clock may also be driven from an external clock source or the
oscillator of another MC14490 (see Figure 5).
NOTE: Immediately after power–up, the outputs of the MC14490
are in indeterminate states.
Diode Protection on All Inputs
Six Debouncers Per Package
Internal Pullups on All Data Inputs
Can Be Used as a Digital Integrator, System Synchronizer, or Delay
Line
Internal Oscillator (R–C), or External Clock Source
TTL Compatible Data Inputs/Outputs
Single Line Input, Debounces Both “Make” and “Break” Contacts
Does Not Require “Form C” (Single Pole Double Throw) Input
Signal
Cascadable for Longer Time Delays
Schmitt Trigger on Clock Input (Pin 7)
Supply Voltage Range = 3.0 V to 18 V
Chip Complexity: 546 FETs or 136.5 Equivalent Gates
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
– 0.5 to +18.0
V
Vin, Vout
Input or Output Voltage Range
(DC or Transient)
– 0.5 to VDD + 0.5
V
Iin
Input Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Ambient Temperature Range
– 55 to +125
°C
Tstg
Storage Temperature Range
– 65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_C From 65_C To 125_C
http://onsemi.com
A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14490DW
SOIC–16
47/Rail
MC14490DWR2
SOIC–16
1000/Tape & Reel
MC14490F
SOEIAJ–16
See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC14490P
AWLYYWW
MC14490FEL
SOEIAJ–16
See Note 1.
MC14490P
PDIP–16
25/Rail
SOIC–16
DW SUFFIX
CASE 751G
1
16
14490
AWLYYWW
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid ap-
plications of any voltage higher than maximum rated
voltages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained to the
range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either VSS or VDD). Unused out-
puts must be left open.
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14490
AWLYWW


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