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MC14076BD bảng dữ liệu(PDF) 1 Page - ON Semiconductor |
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1 / 8 page © Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 3 1 Publication Order Number: MC14076B/D MC14076B 4-Bit D-Type Register with Three-State Outputs The MC14076B 4–Bit Register consists of four D–type flip–flops operating synchronously from a common clock. OR gated output–disable inputs force the outputs into a high–impedance state for use in bus organized systems. OR gated data–disable inputs cause the Q outputs to be fed back to the D inputs of the flip–flops. Thus they are inhibited from changing state while the clocking process remains undisturbed. An asynchronous master root is provided to clear all four flip–flops simultaneously independent of the clock or disable inputs. • Three–State Outputs with Gated Control Lines • Fully Independent Clock Allows Unrestricted Operation for the Two Modes: Parallel Load and Do Nothing • Asynchronous Master Reset • Four Bus Buffer Registers • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable of Driving Two Low–Power TTL Loads or One Low–Power Schottky TTL Load Over the Rated Temperature Range MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) Symbol Parameter Value Unit VDD DC Supply Voltage Range – 0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 2.) 500 mW TA Ambient Temperature Range – 55 to +125 °C Tstg Storage Temperature Range – 65 to +150 °C TL Lead Temperature (8–Second Soldering) 260 °C 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. http://onsemi.com A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week Device Package Shipping ORDERING INFORMATION MC14076BCP PDIP–16 2000/Box MC14076BD SOIC–16 2400/Box MC14076BDR2 SOIC–16 2500/Tape & Reel MARKING DIAGRAMS 1 16 PDIP–16 P SUFFIX CASE 648 MC14076BCP AWLYYWW SOIC–16 D SUFFIX CASE 751B 1 16 14076B AWLYWW |
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