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BZX85C7V5RL bảng dữ liệu(PDF) 7 Page - ON Semiconductor

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Giải thích chi tiết về linh kiện  1 Watt DO-41 Hermetically Sealed Glass Zener Voltage Regulators
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APPLICATION NOTE
Since the actual voltage available from a given zener
diode is temperature dependent, it is necessary to determine
junction temperature under any set of operating conditions
in order to calculate its value. The following procedure is
recommended:
Lead Temperature, TL, should be determined from:
TL = θLAPD + TA.
θLA is the lead-to-ambient thermal resistance (°C/W) and PD
is the power dissipation. The value for
θLA will vary and
depends on the device mounting method.
θLA is generally 30
to 40
°C/W for the various clips and tie points in common use
and for printed circuit board wiring.
The temperature of the lead can also be measured using a
thermocouple placed on the lead as close as possible to the
tie point. The thermal mass connected to the tie point is
normally large enough so that it will not significantly
respond to heat surges generated in the diode as a result of
pulsed operation once steady-state conditions are achieved.
Using the measured value of TL, the junction temperature
may be determined by:
∆TJL is the increase in junction temperature above the lead
temperature and may be found as follows:
TJ = TL + ∆TJL.
∆TJL = θJLPD.
θJL may be determined from Figure 3 for dc power
conditions. For worst-case design, using expected limits of
IZ, limits of PD and the extremes of TJ(∆TJ) may be
estimated. Changes in voltage, VZ, can then be found from:
∆V = θVZ ∆TJ.
θVZ, the zener voltage temperature coefficient, is found
from Figure 2.
Under high power-pulse operation, the zener voltage will
vary with time and may also be affected significantly by the
zener resistance. For best regulation, keep current
excursions as low as possible.
Surge limitations are given in Figure 5. They are lower
than would be expected by considering only junction
temperature, as current crowding effects cause temperatures
to be extremely high in small spots, resulting in device
degradation should the limits of Figure 5 be exceeded.


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