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MC10H016 bảng dữ liệu(PDF) 1 Page - ON Semiconductor |
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MC10H016 bảng dữ liệu(HTML) 1 Page - ON Semiconductor |
1 / 4 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA 2–1 REV 6 © Motorola, Inc. 1996 9/96 4-Bit Binary Counter The MC10H016 is a high–speed synchronous, presettable, cascadable 4–bit binary counter. It is useful for a large number of conversion, counting and digital integration applications. • Counting Frequency, 200 MHz Minimum • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) • Voltage Compensated • MECL 10K–Compatible • Positive Edge Triggered MAXIMUM RATINGS Characteristic Symbol Rating Unit Power Supply (VCC = 0) VEE –8.0 to 0 Vdc Input Voltage (VCC = 0) VI 0 to VEE Vdc Output Current — Continuous — Surge Iout 50 100 mA Operating Temperature Range TA 0 to +75 °C Storage Temperature Range — Plastic — Ceramic Tstg –55 to +150 –55 to +165 °C ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note) 0 ° 25 ° 75 ° Characteristic Symbol Min Max Min Max Min Max Unit Power Supply Current IE — 126 — 115 — 126 mA Input Current High All Except MR Pin 12 MR IinH — — 450 1190 — — 265 700 — — 265 700 µA Input Current Low IinL 0.5 — 0.5 — 0.3 — µA High Output Voltage VOH –1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc Low Output Voltage VOL –1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc High Input Voltage VIH –1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc Low Input Voltage VIL –1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc AC PARAMETERS Propagation Delay Clock to Q Clock to TC MR to Q tpd 1.0 0.7 0.7 2.4 2.4 2.4 1.0 0.7 0.7 2.5 2.5 2.5 1.0 0.7 0.7 2.7 2.6 2.6 ns Set–up Time Pn to Clock CE or PE to Clock tset 2.0 2.5 — — 2.0 2.5 — — 2.0 2.5 — — ns Hold Time Clock to Pn Clock to CE or PE thold 1.0 0.5 — — 1.0 0.5 — — 1.0 0.5 — — ns Counting Frequency fcount 200 — 200 — 200 — MHz Rise Time tr 0.5 2.0 0.5 2.1 0.5 2.2 ns Fall Time tf 0.5 2.0 0.5 2.1 0.5 2.2 ns NOTE: Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. DIP PIN ASSIGNMENT VCC1 Q1 Q0 TC PE CE PO VEE VCC2 Q2 Q3 CP MR P3 P2 P1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 MC10H016 L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 FN SUFFIX PLCC CASE 775–02 TRUTH TABLE CE PE MR CP Function L H L H X X L L H H X X L L L L L H Z Z Z Z ZZ X Load Parallel (Pn to Qn) Load Parallel (Pn to Qn) Count Hold Masters Respond; Slaves Hold Reset (Qn = LOW, TC = HIGH) Z = Clock Pulse (Low to High); ZZ = Clock Pulse (High to Low) Features include assertion inputs and outputs on each of the four master/slave counting flip–flops. Terminal count is generated internally in a manner that allows synchronous loading at nearly the speed of the basic counter. Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–11 of the Motorola MECL Data Book (DL122/D). |
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