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MC10E193 bảng dữ liệu(PDF) 1 Page - ON Semiconductor |
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MC10E193 bảng dữ liệu(HTML) 1 Page - ON Semiconductor |
1 / 4 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA 2–1 REV 3 © Motorola, Inc. 1996 7/96 Error Detection/Correction Circuit The MC10E/100E193 is an error detection and correction (EDAC) circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also provided at the PGEN pin, after Odd/Even parity control and gating with the BPAR input. This output also feeds to a 1-bit shiftable register, for use as part of a scan ring. Used in conjunction with 12-bit parity generators such as the E160, a SECDED (single error correction, double error detection) error system can be designed for a multiple of an 8-bit word. • Hamming Code Generation • 8-Bit Word, Expandable • Provides Parity of Whole Word • Scannable Parity Register • Extended 100E VEE Range of – 4.2V to – 5.46V • 75kΩ Input Pulldown Resistors Pinout: 28-Lead PLCC (Top View) B4 B5 B6 P2 PGEN CLK SHIFT S-IN HOLD EN LOGIC DIAGRAM EV/OD BPAR B0 VEE B1 B2 B3 26 27 28 2 3 4 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 5 6 7 8 9 10 VCCO PARERR PARERR VCC P5 VCCO P4 P3 VCCO P1 B7 B INPUTS 0 3 6 5 7 4 2 1 B2, B3, B6, B7 B1, B3, B5, B7 B4, B5, B6, B7 B1, B2, B4, B7 P2 P1 P3 P4 P5 PGEN BYTE (B0 – B7) PARERR PARERR BPAR EV/OD EN HOLD S-IN SHIFT CLK 0 1 0 1 D 1 * All VCC and VCCO pins are tied together on the die. MC10E193 MC100E193 ERROR DETECTION/ CORRECTION CIRCUIT FN SUFFIX PLASTIC PACKAGE CASE 776-02 |
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