LT8920 datasheet(10/51 Pages) ETC2

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LT8920 Datasheet V1.1

Page 10

Jan. 2017

5. Pin Description

Table 3. Pin Description

QFN24

Pin No.

Pin Name

Type

Description

1, 2, 5, 6, 7,

19, 22

VDD

PWR

Power supply voltage.

3, 4

ANTb, ANT

Balanced RF

RF input/output.

8

FIFO

O

FIFO status indicator bit.

9

GND

Ground connection.

10

VDD_IO

PWR

Vdd for the digital interface.

11

SPI_SS

I

SPI: Enable input for the SPI bus, active low. Also used to bring

device out of SLEEP state.

I2C: Used to bring device out of SLEEP state.

12

BRCLK

O

Output from internal clock

13

PKT

O

Transmit/Receive packet status indicator bit.

14

SPICLK

I

Clock input for SPI/I2C interface.

15

I2C_SEL

I

Mode selection:

0: Interface is SPI

1: Interface is I2C

16

MOSI/A4

I

SPI: Data input for the SPI bus. I2C: Specifies I2C address bit 4.

17

MISO/I2C_DAT

I/O

SPI: Data output (tri-state when not active) I2C: Data in/out

18

RST_n

I

When RST_n is low, most of the chip shuts down to conserve

power. Register values will be lost. To preserve register values,

use SLEEP mode instead.

When raised high, RST_n is used to turn on the chip, restoring all

registers to their default value.

20

LDO_VDD

PWR

Input power to the on-chip LDO.

21

LDO_OUT

PWR

+1.8V output from the on-chip LDO voltage regulator.

Normally this will connect to all VDD pins of the chip, supplying

clean, well-regulated power to all critical sections.

DO NOT CONNECT TO EXTERNAL LOADS.

23

XTALO

A O

Output of the crystal oscillator gain block.

24

XTALI

A I

Input to the crystal oscillator gain block.

25 (Exposed

pad)

GND

Ground reference connection.

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