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LMS6002D bảng dữ liệu(PDF) 7 Page - List of Unclassifed Manufacturers

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© Copyright Lime Microsystems
LMS6002D
LimeLight
7
LMS6002D - Multi-band Multi-standard
Transceiver with Integrated Dual DACs and ADCs
For both TX and RX interfaces IQ_SEL (frame sync) polarity and
interleave mode are independently programmable via the SPI link, see
Figure 8. Here, the frame is defined as two consecutive T(R)X_CLK, i.e.
one T(R)X_IQ_SEL, periods while IQ data from the same sampling
point are present on the multiplexed bus.
I0
Q0
I1
Q1
I2
T(R)XD[11:0]
T(R)X_IQ_SEL
T(R)X_ IQ_SEL
Q0
I0
Q1
I1
Q2
T(R)XD[11:0]
Frame
Positive IQ_SEL polarity
Negative IQ_SEL polarity
IQ interleave mode
QI interleave mode
Frame
Figure 8: Frame sync polarity and interleave modes
Transmitter Data Interface
More detailed functional diagram of the TX data interface is shown in
Figure 9. Corresponding waveforms are given in Figure 10. The
interface is a 12 bit parallel bus from the base band IC carrying
multiplexed IQ data samples for the transmit DACs. The interface data
rate is twice the DACs sample rate. TX_IQ_SEL flag is used to identify I
and Q samples on the multiplexed bus. Note that the DACs sampling
clock is not derived by dividing TX_CLK by two as indicated in Figure 7.
Instead, registered version of TX_IQ_SEL is used. Hence, for the DACs
to receive sampling clock TX_IQ_SEL must be provided and toggled as
in Figure 8. DACs sampling edge is also programmable via SPI link.
The TX digital IQ interface related pins are described as follows:
TX_CLK
TX interface data clock, positive edge
sensitive (input)
TXD[11:0]
12 bit multiplexed IQ data bus (input)
TX_IQ_SEL
Indicates the location of I and Q data on the
multiplexed bus (input)
DAC
D[11:0]
CLK
A[11:0]
B[11:0]
Y[11:0]
D[11:0] Q[11:0]
CLK
A
B
Y
D
Q
CLK
QN
D[11:0] Q[11:0]
CLK
D[11:0] Q[11:0]
CLK
A[11:0]
B[11:0]
Y[11:0]
DAC
D[11:0]
CLK
Dual DAC
TX_CLK/2
tx_fsinc_polarity
dac_clk_pol
tx_interleave_mode
Figure 9: TX data interface
TX_CLK
TX_CLK/2
I_DATA[11:0]
Q_DATA[11:0]
I0
I1
I0
Q0
I1
Q1
TXD[11:0]
TX_IQ_SEL
Q0
Q1
t
SETUP
t
HOLD
External Signals
Internal Signals
Figure 10: TX IQ interface signals
Some examples of the TX interface data rates are provided below:
DACs sample rate
o
WCDMA
15.36 MS/s
o
GSM
1.083 MS/s
TX IQ interface data rate
o
WCDMA
30.72 MS/s
o
GSM
2.167 MS/s
Receiver Data Interface
More detailed functional diagram of the RX data interface is shown in
Figure 11. Corresponding waveforms are given in Figure 12. The
interface is a 12 bit parallel bus output from the LMS6002D to the base
band IC carrying multiplexed IQ data samples from the receive ADCs.
The interface data rate is twice the ADCs sample rate. RX_IQ_SEL flag
is provided to identify I and Q samples on the multiplexed bus. The
receive clock coming from the baseband is on chip divided by two
before being used by the ADC’s. The ADCs sampling edge is also
programmable via SPI link.
RX digital IQ interface related pins are described as follows:
RX_CLK
RX interface data clock, positive edge
sensitive (input)
RXD[11:0]
12 bit multiplexed IQ data bus (output)
RX_IQ_SEL
Indicates the location of I and Q data on the
multiplexed bus (output)
A[11:0]
B[11:0]
Y[11:0]
D[11:0] Q[11:0]
CLK
A
B
Y
D
Q
CLK
QN
rx_interleave_mode
ADC
D[11:0]
CLK
I_DATA[11:0]
Dual ADC
ADC
D[11:0]
CLK
Q_DATA[11:0]
D
Q
CLK
QN
A
B
Y
rx_fsinc_polarity
adc_clk_pol
Divide by 2
RX_CLK/2
Figure 11: RX data interface


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