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LMS6002D bảng dữ liệu(PDF) 4 Page - List of Unclassifed Manufacturers

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LMS6002D bảng dữ liệu(HTML) 4 Page - List of Unclassifed Manufacturers

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LMS6002D
© Copyright Lime Microsystems
RX GAIN CONTROL
The LMS6002D receiver has three gain control elements, RXLNA,
RXVGA1, and RXVGA2 (see Figure 3). RXLNA gain control consists of
a single 6dB step for AGC when large in co-channel blockers are
present and a reduction in system NF is acceptable. The main LNAs
(LNA1 and LNA2) have fine gain control via a 6 bit word which offers
±6dB control intended for frequency correction when large input
bandwidths are required.
RXVGA1 offers 25dB of control range, a 7 bit control word is used and
the response is not log-linear. Maximum step size is 1dB. RXVGA1 is
intended for AGC steps needed to reduce system gain prior to the
channel filters when large in band blockers are present. This gain can
be under control of the baseband or fixed on calibration.
RXVGA2 provides the bulk of gain control for AGC if a constant RX
signal level at the ADC input is required. It has 30dB gain range control
in 3dB steps.
Note: RXLPF has a gain of 0dB when bypassed.
RXLPF
RXMIX
RXPLL
LNA1
RXVGA2
RXVGA1
0
o
90
o
2
2
2
LNA2
LNA3
2
RXLNA
2
Figure 3: RX gain control architecture
Parameter
Condition
Min
Typ
Max
Unit
RXLNA Gain Control Range
Single step
0
6
dB
RXVGA1 Gain Control Range
25
dB
RXVGA1 Gain Step Size
Not log-linear
1
dB
RXLPF Gain
0 dB gain when bypassed
0
6
dB
RXVGA2 Gain Control Range
30
dB
RXVGA2 Gain Step Size
Guaranteed monotonic
3
dB
Table 4: RX gain control
SYNTHESIZERS
LMS6002D has two low phase noise synthesizers to enable full duplex
operation. Both synthesizers are capable of output frequencies up to
3.8GHz. Each synthesizer uses a fractional-N PLL architecture as
shown in Figure 4. The same reference frequency is used for both
synthesisers and is flexible between 23 to 41MHz. The synthesizers
produce a complex output with suitable level to drive IQ mixers in both
the TX and the RX paths.
The LMS6002D can accept clipped sine as well as the CMOS level
signals as the PLL reference clock. Both DC and AC coupling are
supported as shown in Figure 5. Internal buffer self biasing must be
enabled for AC coupling mode. PLL reference clock input can also be
low voltage CMOS (2.5V or 1.8V, for example) which is implemented by
lowering clock buffer supply PVDDSPI33.
PFD
/N
Loop
Filter
VCO
CHP
External
SD
NINT, NFRAC
0
o
90
o
Figure 4: PLL architecture


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