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LMS6002D bảng dữ liệu(PDF) 2 Page - List of Unclassifed Manufacturers |
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2 / 15 page 2 LMS6002D © Copyright Lime Microsystems LMS6002D - Multi-band Multi-standard Transceiver with Integrated Dual DACs and ADCs The top level architecture of LMS6002D transceiver is shown in Figure 1. Both transmitter and receiver are implemented as zero IF architectures providing up to 28MHz modulation bandwidth (equivalent to 14MHz baseband IQ bandwidth). On the transmit side, IQ DAC samples from the baseband processor are provided to the LMS6002D on a 12 bit multiplexed parallel CMOS input level bus. Analog IQ signals are generated by on chip transmit DACs. These are fed to the TXINI and TXINQ inputs. Transmit low pass filters (TXLPF) remove the images generated by zero hold effect of the DACs. The IQ signals are then amplified (TXVGA1) and DC offset is inserted in the IQ path by LO leakage DACs in order to cancel the LO leakage. The IQ signals are then mixed with the transmit PLL (TXPLL) output to produce a modulated RF signal. This RF signal is then split and amplified by two separate variable gain amplifiers (TXVGA2) and two off chip outputs are provided as RF output. Transmitter gain control range of 56dB is provided by IF (TXVGA1, 31dB range) and RF (TXVGA2, 25 dB range) variable gain amplifiers. Both TXVGAs have 1dB gain step control. The LMS6002D provides an RF loop back option (see Figure 1) which enables the TX RF signal to be fed back into the baseband for calibration and test purposes. The RF loop back signal is amplified by an auxiliary PA (AUXPA) in order to increase the dynamic range of the loop. On the receive side, three separate inputs are provided each with a dedicated LNA. Each port preconditioned RF signal is first amplified by a programmable low noise amplifier (RXLNA). The RF signal is then mixed with the receive PLL (RXPLL) output to directly down convert to baseband. Large AGC steps can be implemented by an IF amplifier (RXVGA1) prior to the programmable bandwidth lowpass channel select filters (RXLPF). The received IQ signal is further amplified by a programmable gain amplifier RXVGA2. DC offset is applied at the input of RXVGA2 to prevent saturation and to preserve receive the ADC(s) dynamic range. The resulting analog receive IQ signals are converted into the digital domain using the on chip receive ADCs and provided as an output to the baseband processor on a multiplexed 12 bit CMOS output level parallel bus. The receive clock, RX_CLK, is provided off chip at the RX_CLK_OUT pin and can be used to synchronise with the baseband digital receive data sampling clock. By closing the RXOUT switch and powering down RXVGA2, the RXOUTI and RXOUTQ pins can be used as IQ ADCs inputs. In this configuration the ADCs can be used to measure two external signals, such as an off chip PA temperature sensor or peak detector. Two transmitter outputs (TXOUT1, TXOUT2) and three receiver inputs (RXIN1, RXIN2, RXIN3) are provided to facilitate multi-band operation. The functionality of the LMS6002D is fully controlled by a set of internal registers which can be accessed through a serial port. In order to enable full duplex operation, the LMS6002D contains two separate synthesizers (TXPLL, RXPLL) both driven from the same reference clock source PLLCLK. The PLLCLK signal is provided at the PLLCLKOUT output pin and can be used as the baseband clock. Differential signalling is done in the receive and transmit analog paths throughout the chip. Parameter Condition/Comment Min Typ Max Unit TRX RF Frequency Range 0.3 3.8 GHz Baseband Bandwidth 0.75 14 MHz Frequency Resolution Using 41MHz PLL reference clock 2.4 Hz TRX 3.3V Supply 3.1 3.3 3.5 V TRX 1.8V Supply 1.7 1.8 1.9 V TX Supply Current At maximum gain 280 mA RX Supply Current At maximum gain 220 mA Digital Core Supply Voltage 1.7 1.8 1.9 V Digital Peripheral (IO) Supply Voltage Can go below 3.3V nominal to support LV CMOS signalling 1.7 3.3 3.5 V Ambient Temperature -40 25 85 oC Storage Temperature -65 125 oC Maximum RF Output Power Continuous wave 6 dBm Absolute Maximum RF Input Power No damage 23 dBm PLL Reference Clock For continuous LO frequency range 23 41 MHz PLL Phase Noise 1MHz offset -125 dBc/Hz Table 1: General specifications |
Số phần tương tự - LMS6002D |
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Mô tả tương tự - LMS6002D |
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