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MC100EP809 bảng dữ liệu(PDF) 6 Page - ON Semiconductor

tên linh kiện MC100EP809
Giải thích chi tiết về linh kiện  3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable
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nhà sản xuất  ONSEMI [ON Semiconductor]
Trang chủ  http://www.onsemi.com
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MC100EP809 bảng dữ liệu(HTML) 6 Page - ON Semiconductor

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MC100EP809
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Figure 4. LVPECL Differential Input Levels
GROUND
HSTL OUTPUT Q
Q
50
W
50
W
VIH(DIFF)
VIL(DIFF)
GND
VCCI(LVPECL)
VIH(DIFF)
VIL(DIFF)
GND
VCCO(HSTL)
Figure 5. HSTL Differential Input Levels
Figure 6. HSTL Output Termination and AC Test Reference
VIHCMR
VPP
VPP
VX
Z = 50
W
CLK
CLK
OE
Q
Q
CLK/CLK
D.C. Bias*
Figure 7. HSTL Single–Ended Input Configuration
*Must fall within 680 to 900 mV (Preferably (VIH + VIL)/2).
Figure 8. Output Enable (OE) Timing Diagram
VCCI
Resource Reference of Application Notes
AN1405
ECL Clock Distribution Techniques
AN1406
Designing with PECL (ECL at +5.0 V)
AND8002
Marking and Date Codes
AND8009
ECLinPS Plus Spice I/O Model Kit
AND8020
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.


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