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MC1066DBR2 bảng dữ liệu(PDF) 2 Page - ON Semiconductor |
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MC1066DBR2 bảng dữ liệu(HTML) 2 Page - ON Semiconductor |
2 / 16 page MC1066 http://onsemi.com 2 FUNCTIONAL BLOCK DIAGRAM Int. Temp Ext.Temp Status Byte Config. Byte Conv. Rate Ext. Hi Limit Ext. Lo Limit Int. Hi Limit Int. Lo Limit Register Set Modulator DS Internal Sensor (Diode) Control Logic SMBus Interface OS STBY SCL SDA ADD 0 ADD 1 CRIT. Limit CRIT 0 CRIT 1 INT_SEL ALERT/ COMP D+ D– PIN DESCRIPTION Pin No. Symbol Type Description 2 VDD Power Power Supply Input 3 D+ Bi–Directional Current Source and A/D Positive Input 4 D– Bi–Directional Current Sink and A/D Negative Input 6, 10 ADD[1:0] Input Address Select Pins (See Address Decode Table) 7, 8 GND Power System Ground 11 ALERT/COMP Output SMBus Interrupt (SMBALERT) or Comparator Output 12 SDA Bi–Directional SMBus Serial Data 14 SCL Input SMBus Serial Clock 15 STBY Input Standby Enable 1, 5 CRIT[1:0] Input CRITICAL Setpoint Bits (See CRITICAL Setpoint Decode Table) 9 OS Output Open Collector, Low–True “Over–Temperature” Warning Output 13 INT_SEL Input Selects ALERT or COMP Output on Pin 11 16 NC — Not Connected PIN DESCRIPTION SCL Input. SMBus serial clock. Clocks data into and out of the MC1066. SDA Bidirectional. Serial data is transferred on the SMBus in both directions using this pin. ADD1, ADD0 Inputs. Sets the 7–bit SMBus address. These pins are “tri–state,” and the SMBus addresses are specified in the Address Decode Table. (NOTE: The tri–state scheme allows up to nine MC1066s on a single bus. A match between the MC1066’s address and the address specified in the serial bit stream must be made to initiate communication. Many SMBus–compatible devices with other addresses may share the same 2–wire bus. These pins are only active at power–on reset, and will latch into the appropriate states. ALERT/COMP* Output, Open Collector, Active Low. The ALERT output corresponds to the general SMBALERT signal and indicates an interrupt event. The MC1066 will respond to the standard SMBus Alert Response Address when ALERT is asserted. Normally, the ALERT output will be asserted and latched when any of the following occurs: |
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