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MC10161 bảng dữ liệu(PDF) 1 Page - ON Semiconductor |
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1 / 5 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3–73 REV 5 © Motorola, Inc. 1996 3/93 Binary to 1-8 Decoder (Low) The MC10161 is designed to decode a three bit input word to a one of eight line output. The selected output will be low while all other outputs will be high. The enable inputs, when either or both are high, force all outputs high. The MC10161 is a true parallel decoder. No series gating is used internally, eliminating unequal delay times found in other decoders. This design provides the identical 4 ns delay from any address or enable input to any output. A complete mux/demux operation on 16 bits for data distribution is illustrated in Figure 1. This system, using the MC10136 control counters, has the capability of incrementing, decrementing or holding data channels. When both S0 and S1 are low, the index counters reset, thus initializing both the mux and demux units. The four binary outputs of the counter are buffered by the MC10101s to send twisted–pair select data to the multiplexer/demultiplexer to units. PD = 315 mW typ/pkg (No Load) tpd = 4.0 ns typ tr, tf = 2.0 ns typ (20%–80%) LOGIC DIAGRAM VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 E0 2 E1 15 A7 B9 C14 6Q0 5Q1 4Q2 3Q3 13 Q4 12 Q5 11 Q6 10 Q7 TRUTH TABLE ENABLE INPUTS INPUTS OUTPUTS E1 E0 C B A Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 L L L L L L H H H H H H H L L L L H H L H H H H H H L L L H L H H L H H H H H L L L H H H H H L H H H H L L H L L H H H H L H H H L L H L H H H H H H L H H L L H H L H H H H H H L H L L H H H H H H H H H H L H X X X X H H H H H H H H X H X X X H H H H H H H H MC10161 DIP PIN ASSIGNMENT VCC1 E0 Q3 Q2 Q1 Q0 A VEE VCC2 E1 C Q4 Q5 Q6 Q7 B 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–11 of the Motorola MECL Data Book (DL122/D). L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 FN SUFFIX PLCC CASE 775–02 |
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