MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

3–41

REV 5

3/93

Bi-Quinary Counter

The MC10138 is a four bit counter capable of divide by two, five, or ten

functions. It is composed of four set–reset master–slave flip–flops. Clock

inputs trigger on the positive going edge of the clock pulse.

Set or reset input override the clock, allowing asynchronous “set” or

“clear.” Individual set and common reset inputs are provided, as well as

complementary outputs for the first and fourth bits.

PD = 370 mW typ/pkg (No Load)

ftog = 150 MHz typ

tr, tf = 2.5 ns typ (20%–80%)

2

LOGIC DIAGRAM

VCC1 = PIN 1; VCC2 = PIN 16; VEE = PIN 8

11

S0

Q0

Q0

14

9

12

Clock

Reset

D1

C1

R

Q

Q

S

15

Q’

10

S1

Q1

D1

C2

R

Q

Q

S

13

Q’

D2

C2

7

6

S2

Q2

D1

C2

R

Q

Q

S

4

Q’

C1

5

S3

Q3

Q3

3

D1

C2

R

Q’

Q

S

Q

D2

COUNTER TRUTH TABLES

BI–QUINARY

(Clock connected to C2

and Q3 connected to C1)

BCD

(Clock connected to C1

and Q0 connected to C2)

COUNT

Q1

Q2

Q3

Q0

COUNT

Q0

Q1

Q2

Q3

0

L

L

L

L

0

L

L

L

L

1

H

L

L

L

1

H

L

L

L

2

L

H

L

L

2

L

H

L

L

3

H

H

L

L

3

H

H

L

L

4

L

L

H

L

4

L

L

H

L

5

L

L

L

H

5

H

L

H

L

6

H

L

L

H

6

L

H

H

L

7

L

H

L

H

7

H

H

H

L

8

H

H

L

H

8

L

L

L

H

9

L

L

H

H

9

H

L

L

H

COUNTER STATE DIAGRAM — POSITIVE LOGIC

0

4

71

32

6

5

98

7

65

11

13

12

10

15

14

01

2

3

4

CLOCK CONNECTED TO C2

Q0 CONNECTED TO C2

MC10138

DIP

PIN ASSIGNMENT

VCC1

Q3

Q3

Q2

S3

S2

C2

VEE

VCC2

Q0

Q0

Q1

C1

S0

S1

RESET

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

L SUFFIX

CERAMIC PACKAGE

CASE 620–10

P SUFFIX

PLASTIC PACKAGE

CASE 648–08

FN SUFFIX

PLCC

CASE 775–02

Pin assignment is for Dual–in–Line Package.

For PLCC pin assignment, see the Pin Conversion

Tables on page 6–11 of the Motorola MECL Data

Book (DL122/D).