MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

4–1

REV 2

7/97

Triple PECL to LVPECL

Translator

The MC100LVEL92 is a triple PECL to LVPECL translator. The device

receives standard PECL signals and translates them to differential

LVPECL output signals.

A PECL VBB output is provided for interfacing single ended PECL

signals at the inputs. If a single ended PECL input is to be used the PECL

VBB output should be connected to the D input and the active signal will

drive the D input. When used the PECL VBB should be bypassed to

ground via a 0.01

µf capacitor. The PECL VBB is designed to act as a

switching reference for the MC100LVEL92 under single ended input

conditions, as a result the pin can only source/sink 0.5mA of current.

To accomplish the PECL to LVPECL level translation, the

MC100LVEL92 requires three power rails. The VCC supply is to be

connected to the standard PECL supply, the LVCC supply is to be

connected to the LVPECL supply, and Ground is connected to the system

ground plane. Both the VCC and LVCC should be bypassed to ground

with a 0.01

µf capacitor.

Under open input conditions, the D input will be biased at a VCC/2

voltage level and the D input will be pulled to ground. This condition will

force the “Q” output low, ensuring stability.

D2

D1

Logic Diagram and Pinout: 20-Lead SOIC (Top View)

D1

17

18

16

15

14

13

12

4

3

5678

9

Q0

11

10

Q1

Q1

Q2

Q2

VCC

D0

19

20

2

1

VCC

Q0

D0

D2

VCC

GND

LVCC

PECL

VBB

LVCC

PECL

VBB

PECL

LVPECL

PECL

LVPECL

PECL

LVPECL

MC100LVEL92

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D-04

1

20

PIN NAMES

Function

PECL Inputs

LVPECL Outputs

PECL Reference Voltage Output

VCC for LVPECL Output

VCC for PECL Inputs

Common Ground Rail

Pins

Dn

Qn

VBB

LVCC

VCC

GND