MC10EP29 datasheet(1/8 Pages) ONSEMI

tên linh kiện	MC10EP29

Giải thích chi tiết về linh kiện	3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset

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September, 2002 – Rev. 2

1

Publication Order Number:

MC10EP29/D

MC10EP29, MC100EP29

3.3V / 5VECL Dual

Differential Data and Clock

D Flip-Flop With Set and

Reset

The MC10/100EP29 is a dual master–slave flip–flop. The device

features fully differential Data and Clock inputs as well as outputs.

The MC10/100EP29 is functionally equivalent to the

MC10/100EL29. Data enters the master latch when the clock is LOW

and transfers to the slave upon a positive transition on the clock input.

The differential inputs have special circuitry which ensures device

stability under open input conditions. When both differential inputs

are left open the D input will pull down to VEE and the D input will

bias around VCC/2. The outputs will go to a defined state, however the

state will be random based on how the flip flop powers up.

Both flip flops feature asynchronous, overriding Set and Reset

inputs. Note that the Set and Reset inputs cannot both be HIGH

simultaneously.

The VBB pin, an internally generated voltage supply, is available to

this device only. For single-ended input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB

and VCC via a 0.01

mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, VBB should be left open.

The 100 Series contains temperature compensation.

• Maximum Frequency > 3 GHz Typical

• 500 ps Typical Propagation Delays

• PECL Mode Operating Range: V

CC = 3.0 V to 5.5 V

with VEE = 0 V

• NECL Mode Operating Range: V

CC = 0 V

with VEE = –3.0 V to –5.5 V

• Open Input Default State

• Safety Clamp on Inputs

MARKING

DIAGRAM*

TSSOP–20

DT SUFFIX

CASE 948E

Device

Package

Shipping

ORDERING INFORMATION

MC10EP29DT

TSSOP–20

75 Units/Rail

MC10EP29DTR2

TSSOP–20 2500 Tape & Reel

xxx = MC10 or 100

A

= Assembly Location

L

= Wafer Lot

Y

= Year

W

= Work Week

*For additional information, see Application Note

AND8002/D

xxx

EP29

ALYW

20

1

MC100EP29DT

TSSOP–20

75 Units/Rail

MC100EP29DTR2 TSSOP–20 2500 Tape & Reel

1

20

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Số phần tương tự - MC10EP29

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
ON Semiconductor	MC10EP29	173Kb / 11P	3.3V / 5V ECL Dual Differential Data and Clock D Flip?묯lop With Set and Reset December, 2006 ??Rev. 4
	MC10EP29	111Kb / 10P	ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset April, 2014 ??Rev. 9
	MC10EP29DT	173Kb / 11P	3.3V / 5V ECL Dual Differential Data and Clock D Flip?묯lop With Set and Reset December, 2006 ??Rev. 4
	MC10EP29DTG	173Kb / 11P	3.3V / 5V ECL Dual Differential Data and Clock D Flip?묯lop With Set and Reset December, 2006 ??Rev. 4
	MC10EP29DTG	111Kb / 10P	ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset April, 2014 ??Rev. 9

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Mô tả tương tự - MC10EP29

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Micrel Semiconductor	SY10EP53V	52Kb / 5P	5V/3.3V DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP WITH SET AND RESET
ON Semiconductor	MC10EP131	90Kb / 10P	3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock January, 2004 ??Rev. 7
Micrel Semiconductor	SY10EP53V	86Kb / 6P	5V/3.3V DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP WITH SET AND RESET
Micrel Semiconductor	SY10EP53V	64Kb / 6P	5V/3.3V DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP WITH SET AND RESET
ON Semiconductor	MC10EP29	111Kb / 10P	ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset April, 2014 ??Rev. 9
	MC10EP29	173Kb / 11P	3.3V / 5V ECL Dual Differential Data and Clock D Flip?묯lop With Set and Reset December, 2006 ??Rev. 4
	MC10EP51	76Kb / 8P	3.3V / 5V ECL D Flip-Flop with Reset and Differential Clock April, 2001 ??Rev. 3
Micrel Semiconductor	SY100EL29V	65Kb / 4P	5V/3.3V DUAL DIFFERENTIAL DATA AND CLOCK D FLIP-FLOP w/SET AND RESET
ON Semiconductor	MC100EL29	116Kb / 6P	5V ECL Dual Differential Data and Clock D Flip?묯lop With Set and Reset October, 2006 ??Rev. 4
ON Semiconductor	MC100LVEL29	120Kb / 6P	3.3V ECL Dual Differential Data and Clock D Flip?묯lop With Set and Reset November, 2006 ??Rev. 5

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