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MC100LVEL32DR2 bảng dữ liệu(PDF) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2000
April, 2000 – Rev. 1
1
Publication Order Number:
MC100LVEL32/D
MC100LVEL32
÷2 Divider
The MC100LVEL32 is an integrated
÷2 divider. The differential
clock inputs and the VBB allow a differential, single-ended or AC
coupled interface to the device. If used, the VBB output should be
bypassed to ground with a 0.01
µF capacitor. Also note that the VBB is
designed to be used as an input bias on the LVEL32 only, the VBB
output has limited current sink and source capability.The LVEL32 is
functionally identical to the EL32, but operates from a low voltage
supply.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flop will attain a random state; the
reset allows for the synchronization of multiple EL32’s in a system.
510ps Propagation Delay
3.0GHz Toggle Frequency
High Bandwidth Output Transitions
75kΩ Internal Input Pulldown Resistors
>1000V ESD Protection
4
3
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
1
2
5
6
7
8
Q
VEE
VCC
Q
CLK
VBB
R
÷2
Reset
CLK
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC100LVEL32D
SO–8
98 Units/Rail
MC100LVEL32DR2
SO–8
2500 Tape & Reel
PIN
FUNCTION
CLK
Clock Inputs
Reset
Asynch Reset
VBB
Ref Voltage Output
Q
Data Ouputs
PIN DESCRIPTION
SO–8
D SUFFIX
CASE 751
MARKING DIAGRAM
1
8
*For additional information, see Application Note
AND8002/D
ALYW
KVL32
1
8
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week


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