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MC100EP139 bảng dữ liệu(PDF) 1 Page - ON Semiconductor |
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MC100EP139 bảng dữ liệu(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 1 1 Publication Order Number: MC100EP139/D MC100EP139 Product Preview ÷2/4, ÷4/5/6 Clock Generation Chip The MC100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single–ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a single–ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01 µF capacitor. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip–flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip–flops will attain a random state; therefore, for systems which utilize multiple EP139s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one EP139, the MR pin need not be exercised as the internal divider design ensures synchronization between the ÷2/4 and the ÷4/5/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. • 50ps Output–to–Output Skew • PECL mode: 3.0V to 5.5V VCC with VEE = 0V • ECL mode: 0V VCC with VEE = –3.0V to –5.5V • Synchronous Enable/Disable • Master Reset for Synchronization of Multiple Chips • Q Output will default LOW with inputs open or at VEE • ESD Protection: >2KV HBM, >100V MM • VBB Output • New Differential Input Common Mode Range • Moisture Sensitivity Level 2 For Additional Information, See Application Note AND8003/D • Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34 • Transistor Count = 758 devices This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. TSSOP–20 DT SUFFIX CASE 948E http://onsemi.com Device Package Shipping ORDERING INFORMATION MC100EP139DT TSSOP 75 Units/Rail MARKING DIAGRAM MC100EP139DTR2 TSSOP 2500 Tape/Reel SO–20 DW SUFFIX CASE 751D MC100EP139DW SOIC 38 Units/Rail MC100EP139DWR2 SOIC 2500 Tape/Reel *For additional information, see Application Note AND8002/D KEP 139 ALYW A = Assembly Location L = Wafer Lot Y = Year W = Work Week MC100EP139 AWLYWW A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week |
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