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MTV038N20 bảng dữ liệu(PDF) 5 Page - List of Unclassifed Manufacturers

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Giải thích chi tiết về linh kiện  On-Screen Display Controller for CRT/LCD Monitor
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MTV038N20 bảng dữ liệu(HTML) 5 Page - List of Unclassifed Manufacturers

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Revision 1.1
-5-
2001/8/21
MTV038
(Revision 1.1)
MYSON
TECHNOLOGY
the format (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with
dummy data.
TABLE 1. The Configuration of Transmission Formats
There are 2 types of data which should be accessed through the serial data interface, one is ADDRESS bytes
of display registers, and the other is ATTRIBUTE bytes of display registers, the protocols are same for all
except the bit5 of row address and the bit5 of column address. The MSB(b7) is used to distinguish row and
column addresses when transferring data from external controller. The bit6 of column address is used to dif-
ferentiate the column address for format (a), (b) and format (c) respectively. Bit5 of row address for display
register is used to distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1".
And at address bytes, bit5 of column address is the MSB (bit8) and data bytes are the 8 LSB (bit7~bit0)
of display fonts address to save half MCU memory for true 512 fonts display. So each one of the 512 fonts
can be displayed at the same time (see Table 1). And for format (c), since D8 is filled while program column
address of address bytes, the continued data will be the same bank of upper 256 fonts or lower 256 fonts until
program column address of address bytes again.
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format
(a) and (c), but not from format (c) back to format (a) and (b). The alternation between transmission formats is
configured as the state diagram shown in Figure 3.
Address
b7
b6
b5
b4
b3
b2
b1
b0
Format
Address Bytes
of Display Reg.
Row
1
0
0
R4
R3
R2
R1
R0
a,b,c
Columnab
0
0
D8
C4
C3
C2
C1
C0
a,b
Columnc
0
1
D8
C4
C3
C2
C1
C0
c
Data
D7
D6
D5
D4
D3
D2
D1
D0
a,b,c
Attribute Bytes
of Display Reg.
Row
1
0
1
R4
R3
R2
R1
R0
a,b,c
Columnab
0
0
x
C4
C3
C2
C1
C0
a,b
Columnc
0
1
x
C4
C3
C2
C1
C0
c
Data
D7
D6
D5
D4
D3
D2
D1
D0
a,b,c
Initiate
ROW
COL
c
COL
ab
DA
c
DA
ab
1, X
0,
1
0,
0
X,
X
X,
X
0,
1
1, X
1, X
format (a)
format (b)
format (c)
X, X
0, X
Input = b7, b6
0, 0
FIGURE 3. Transmission State Diagram


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