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LM4702C bảng dữ liệu(PDF) 6 Page - National Semiconductor (TI) |
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LM4702C bảng dữ liệu(HTML) 6 Page - National Semiconductor (TI) |
6 / 15 page Electrical Characteristics (LM4702A) Vcc = +85V, Vee = –85V (Pre-release information) (Notes 1, 2) The following specifications apply for I MUTE = 1.5mA, unless otherwise specified. Limits apply for TA = 25˚C. Symbol Parameter Conditions LM4702 Units (Limits) Typical Limit (Note 6) (Notes 7, 8) I CC Total Quiescent Power Supply Current V CM = 0V, VO = 0V, IO = 0A 27 TBD mA (max) THD+N Total Harmonic Distortion + Noise No load, A V = 30dB V OUT = 20VRMS @ 1kHz 0.001 TBD % (max) R S Input Bias Resistor 50 TBD k Ω (max) Av Closed Loop Voltage Gain TBD dB (min) Av open Open Loop Gain Vin = 1mVrms, f = 1KHz, C = 30pF 93 dB Vom Output Voltage Swing THD = 0.05%, Freq = 20Hz to 20KHz 57 TBD Vrms (min) Vnoise Output Noise Rs = 10k Ω, LPF = 30kHz, Av = 30dB A-weighted 100 80 TBD TBD µV (max) I OUT Output Current Outputs Shorted 5.5 TBD TBD mA(min) mA (max) I mute Current into Mute Pin To put part in “play” mode 1.5 TBD TBD mA(min) mA (max) X TALK Channel Separation (Note 11) f = 1kHz at Av = 30dB 90 TBD dB (min) SR Slew Rate V IN = 1.2VP-P, f = 10kHz square Wave, Outputs shorted TBD TBD V/µs (min) V OS Input Offset Voltage V CM = 0V, IO = 0mA 5 TBD mV (max) I B Input Bias Current V CM = 0V, IO = 0mA 150 TBD nA (max) PSRR Power Supply Rejection Ratio Rs = 1k, f = 100Hz, Vripple = 1Vrms, Input Referred 110 TBD dB (min) Note 1: All voltages are measured with respect to the ground pins, unless otherwise specified. Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test condition which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given. However, the typical value is a good indication of device’s performance. Note 3: The maximum power dissipation must be de-rated at elevated temperatures and is dictated by TJMAX, θJC, and the ambient temperature TA. The maximum allowable power dissipation is PDMAX =(TJMAX -TA)/θJC or the number given in the Absolute Maximum Ratings, whichever is lower. For the LM4702, TJMAX = 150˚C and the typical θJC is 1˚C/W. Refer to the Thermal Considerations section for more information. Note 4: Human body model, 100pF discharged through a 1.5k Ω resistor. Note 5: Machine Model: a 220pF - 240pF discharged through all pins. Note 6: Typical specifications are measured at 25˚C and represent the parametric norm. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Note 9: The maximum operating junction temperature is 150˚C. Note 10: PCB layout will affect cross talk. It is recommended that input and output traces be separated by as much distance as possible. Return ground traces from outputs should be independent back to a single ground point and use as wide of traces as possible. Note 11: The TA15A is a non-isolated package. The package’s metal back and any heat sink to which it is mounted are connected to the Vee potential when using only thermal compound. If a mica washer is used in addition to thermal compound, θCS (case to sink) is increased, but the heat sink will be electrically isolated from Vee. www.national.com 6 |
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