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MTV230M64
Page 6 of 31
3. Chip Configuration
The Chip Configuration registers define the chip pins function, as well as the functional blocks' connection,
configuration and frequency.
Reg name
addr
bit7
bit6
bit5
Bit4
bit3
bit2
bit1
bit0
PADMOD
F2Bh (w)
HIICE
IIICE
HVE
HclpE
FclkE
P62E
PADMOD
F2Ch (w)
DA3EDA2EDA1EDA0EAD3E
AD2EAD1EAD0E
PADMOD
F2Dh (w)
P47oe
P46oe
P45oe
P44oe
P43oe
P42oe
P41oe
P40oe
PADMOD
F2Eh (w)
P57oe
P56oe
P55oe
P54oe
P53oe
P52oe
P51oe
P50oe
OPTION
F2Fh (w)
PWMF
DIV253 SlvAbs1 SlvAbs0 ENSCL
Msel
MIICF1
MIICF0
PADMOD (w) : Pad mode control registers. (All are "0" in Chip Reset)
HIICE = 1
→ pin “P3.0/Rxd/HSCL” is HSCL;
pin “P3.1/Txd/HSDA” is HSDA
= 0
→ pin “P3.0/Rxd/HSCL” is P3.0/Rxd;
pin “P3.1/Txd/HSDA” is P3.1/Txd
IIICE
= 1
→ pin “P6.1/ISDA” is ISDA;
pin “P6.0/ISCL” is ISCL
= 0
→ pin “P6.1/ISDA” is P6.1;
pin “P6.0/ISCL” is P6.0
HVE
= 1
→ pin “P4.7/VBLANK” is VBLANK;
pin “P4.6/HBLANK” is HBLANK
= 0
→ pin “P4.7/VBLANK” is P4.7;
pin “P4.6/HBLANK” is P4.6
HclpE = 1
→ pin “P4.5/HCLAMP” is HCLAMP
= 0
→ pin “P4.5/HCLAMP” is P4.5
FclkE = 1
→ CPU running at double rate
= 0
→ CPU running at normal rate
P62E
= 1
→ pin “INT/P6.2” is P6.2
= 0
→ pin “INT/P6.2” is INT
DA3E = 1
→ pin “P5.7/DA3” is DA3
= 0
→ pin “P5.7/DA3” is P5.7
DA2E = 1
→ pin “P5.6/DA2” is DA2
= 0
→ pin “P5.6/DA2” is P5.6
DA1E = 1
→ pin “P5.5/DA1” is DA1
= 0
→ pin “P5.5/DA1” is P5.5
DA0E = 1
→ pin “P5.4/DA0” is DA0
= 0
→ pin “P5.4/DA0” is P5.4
AD3E = 1
→ pin “P5.3/AD3” is AD3
= 0
→ pin “P5.3/AD3” is P5.3
AD2E = 1
→ pin “P5.2/AD2” is AD2
= 0
→ pin “P5.2/AD2” is P5.2
AD1E = 1
→ pin “P5.1/AD1” is AD1
= 0
→ pin “P5.1/AD1” is P5.1
AD0E = 1
→ pin “P5.0/AD0” is AD0
= 0
→ pin “P5.0/AD0” is P5.0
P47oe = 1
→ P4.7 is output pin
= 0
→ P4.7 is input pin
P46oe = 1
→ P4.6 is output pin
= 0
→ P4.6 is input pin
P45oe = 1
→ P4.5 is output pin
= 0
→ P4.5 is input pin
P44oe = 1
→ P4.4 is output pin
= 0
→ P4.4 is input pin
P43oe = 1
→ P4.3 is output pin
= 0
→ P4.3 is input pin
P42oe = 1
→ P4.2 is output pin
= 0
→ P4.2 is input pin