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Giải thích chi tiết về linh kiện  These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary planar stripe, DMOS technology
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nhà sản xuất  FAIRCHILD [Fairchild Semiconductor]
Trang chủ  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FQD6N50C bảng dữ liệu(HTML) 4 Page - Fairchild Semiconductor

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Rev. B, June 2004
©2004 Fairchild Semiconductor Corporation
Typical Characteristics (Continued)
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current
vs Case Temperature
Figure 11. Transient Thermal Response Curve
t1
PDM
t2
Figure 7. Breakdown Voltage Variation
vs Temperature
Figure 8. On-Resistance Variation
vs Temperature
-100
-50
0
50
100
150
200
0.8
0.9
1.0
1.1
1.2
Notes :
1. V
GS = 0 V
2. I
D = 250 µA
T
J, Junction Temperature [
oC]
-100
-50
0
50
100
150
200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Notes :
1. V
GS = 10 V
2. I
D = 2.25 A
T
J, Junction Temperature [
oC]
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
-2
10
-1
10
0
N o te s :
1 . Z
θ JC (t) = 2 . 0 5
/W M a x .
2 . D uty Fa c to r, D = t
1/t 2
3 . T
JM - T C = P DM * Z θ JC (t)
sin g le p u lse
D= 0 .5
0.02
0.2
0.0 5
0.1
0.01
t
1, S quare W a v e P u l s e D u ra tion [s ec ]
25
50
75
100
125
150
0
1
2
3
4
5
T
C, Case Temperature [
]
10
0
10
1
10
2
10
3
10
-2
10
-1
10
0
10
1
10
2
100 ms
1 ms
DC
10 ms
100
µs
Operation in This Area
is Limited by R
DS(on)
Notes :
1. T
C = 25
oC
2. T
J = 150
oC
3. Single Pulse
V
DS, Drain-Source Voltage [V]


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