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MVTX2601 bảng dữ liệu(PDF) 9 Page - Zarlink Semiconductor Inc |
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MVTX2601 bảng dữ liệu(HTML) 9 Page - Zarlink Semiconductor Inc |
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9 / 91 page  MVTX2601 Data Sheet 9 Zarlink Semiconductor Inc. 1.0 Block Functionality 1.1 Frame Data Buffer (FDB) Interfaces The FDB interface supports pipelined synchronous burst SRAM (SBRAM) memory at 100 MHz. To ensure a non- blocking switch, one memory domain with a 64 bit wide memory bus is required. At 100 MHz, the aggregate memory bandwidth is 6.4 Gbps, which is enough to support 24 10/100 Mbps. The Switching Database is also located in the external SBRAM; it is used for storing MAC addresses and their physical port number. 1.2 10/100 MAC Module (RMAC) The 10/100 Media Access Control module provides the necessary buffers and control interface between the Frame Engine (FE) and the external physical device (PHY). The MVTX2601 has two interfaces, RMII or Serial (only for 10 M). The 10/100 MAC of the MVTX2601 device meets the IEEE 802.3 specification. It is able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for up to 16 total transmissions. The PHY addresses for 24 10/100 MAC are from 08h to 1Fh. 1.3 Configuration Interface Module The MVTX2601 supports a serial and an I2C interface, which provides an easy way to configure the system. Once configured, the resulting configuration can be stored in an I2C EEPROM. 1.4 Frame Engine The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, sent to the search engine to resolve the destination port. The arriving frame is moved to the FDB. After receiving a switch response from the search engine, the frame engine performs transmission scheduling based on the frame’s priority. The frame engine forwards the frame to the MAC module when the frame is ready to be sent. 1.5 Search Engine The Search Engine resolves the frame’s destination port or ports according to the destination MAC address (L2). It also performs MAC learning, priority assignment and trunking functions. 1.6 LED Interface The LED interface provides a serial interface for carrying 24 port status signals. 1.7 Internal Memory Several internal tables are required and are described as follows: • Frame Control Block (FCB) - Each FCB entry contains the control information of the associated frame stored in the FDB, e.g., frame size, read/write pointer, transmission priority, etc. • MCT Link Table - The MCT Link Table stores the linked list of MCT entries that have collisions in the external MAC Table. The external MAC table is located in the FDB Memory. Note: the external MAC table is located in the external SBRAM Memory. |
Số phần tương tự - MVTX2601 |
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Mô tả tương tự - MVTX2601 |
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