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AD5201BRM10-REEL7 bảng dữ liệu(PDF) 4 Page - Analog Devices

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Giải thích chi tiết về linh kiện  256-Position and 33-Position Digital Potentiometers
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AD5201BRM10-REEL7 bảng dữ liệu(HTML) 4 Page - Analog Devices

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REV. B
–4–
AD5200/AD5201–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
1
Max
Unit
INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 2, 3])
Input Clock Pulsewidth
tCH, tCL
Clock Level High or Low
20
ns
Data Setup Time
tDS
5ns
Data Hold Time
tDH
5ns
CS Setup Time
tCSS
15
ns
CS High Pulsewidth
tCSW
40
ns
CLK Fall to
CS Fall Hold Time
tCSH0
0ns
CLK Fall to
CS Rise Hold Time
tCSH1
0ns
CS Rise to Clock Rise Setup
tCS1
10
ns
NOTES
1Typicals represent average readings at 25
°C and V
DD = 5 V, VSS = 0 V.
2Guaranteed by design and not subject to production test.
3See timing diagram for location of measured values. All input control voltages are specified with t
R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of
1.5 V. Switching characteristics are measured using VLOGIC = 5 V.
Specifications subject to change without notice.
(VDD = 5 V
10%, or 3 V
10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40 C < TA < +85 C
unless otherwise noted.)
D7
D6
D5
D4
D3
D2
D1
D0
0
1
SDI
0
1
CLK
0
1
VOUT
0
1
CS
DAC REGISTER LOAD
Figure 1a. AD5200 Timing Diagram
0
1
SDI
D5
D4D3
D2D1
D0
0
1
CLK
0
1
CS
DAC REGISTER LOAD
0
1
VOUT
Figure 1b. AD5201 Timing Diagram
Dx
Dx
0
1
0
1
0
1
0
VDD
SDI
(DATA IN)
CLK
CS
VOUT
t
CH
t
DS
t
DH
t
CS1
t
CSW
t
S
t
CL
t
CSH0
t
CSS
1LSB
t
CSH1
Figure 1c. Detail Timing Diagram


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