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AD5428 bảng dữ liệu(PDF) 5 Page - Analog Devices

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AD5428 bảng dữ liệu(HTML) 5 Page - Analog Devices

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AD5429/AD5439/AD5449
Rev. 0 | Page 5 of 32
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V, VREF = 5 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
See Figure 2 and Figure 3. Temperature range for Y version is −40°C to +125°C. Guaranteed by design and characterization, not subject to
production test. All input signals are specified with tr = tf = ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Table 2.
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments1
fSCLK
50
MHz max
Max clock frequency
t1
20
ns min
SCLK cycle time
t2
8
ns min
SCLK high time
t3
8
ns min
SCLK low time
t4
13
ns min
SYNC falling edge to SCLK falling edge setup time
t5
5
ns min
Data setup time
t6
4
ns min
Data hold time
t7
5
ns min
SYNC rising edge to SCLK falling edge
t8
30
ns min
Minimum SYNC high time
t9
0
ns min
SCLK falling edge to LDAC falling edge
t10
12
ns min
LDAC pulse width
t11
10
ns min
SCLK falling edge to LDAC rising edge
t122
25
ns min
SCLK active edge to SDO valid, strong SDO driver
60
ns min
SCLK active edge to SDO valid, weak SDO driver
1 Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.
2 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 4.


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