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CD1284 bảng dữ liệu(PDF) 8 Page - Intel Corporation |
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CD1284 bảng dữ liệu(HTML) 8 Page - Intel Corporation |
8 / 176 page CD1284 — IEEE 1284-Compatible Parallel Interface Controller 8 Datasheet Figures 1 Functional Block Diagram ................................................................................... 11 2 CD1284 Sample System Block Diagram ............................................................ 14 3 CD1284 Functional Block Diagram ..................................................................... 32 4 Internal Address Generation ............................................................................... 32 5 Control Signal Generation ................................................................................... 38 6 CD1284 Daisy-Chain Connections ..................................................................... 42 7 Interrupt Generation Logic .................................................................................. 45 8 FIFO Timer Processing ....................................................................................... 53 9 CD1284 Receive Character Processing ............................................................. 64 10 CD1284 Transmit Character Processing ............................................................ 70 11 FIFO Data Path Functional Diagram — Receive ................................................ 78 12 FIFO Data Path Functional Diagram — Transmit ............................................... 80 13 Cable Connection................................................................................................ 85 14 External Buffer Control........................................................................................ 86 15 Intel‚ 80x86 Family Interface ............................................................................... 87 16 Motorola‚ 68020 Interface ................................................................................... 88 17 National Semiconductor‚ 32000 Interface ........................................................... 89 18 Flow Diagram of CD1284 Master Initialization Sequence ................................... 92 19 Polling Flow Chart ............................................................................................. 100 20 Reset Timing ..................................................................................................... 158 21 Clock Timing ..................................................................................................... 159 22 Asynchronous Read Cycle Timing .................................................................... 159 23 Asynchronous Write Cycle Timing .................................................................... 160 24 Asynchronous Service Acknowledge Cycle Timing .......................................... 161 25 Asynchronous DMA Read Cycle Timing ........................................................... 162 26 Asynchronous DMA Read Cycle Timing (Two Back-to-Back DMA Reads) ...... 162 27 Asynchronous DMA Write Cycle Timing ........................................................... 163 28 Asynchronous DMA Write Cycle Timing (Two Back-to-Back DMA Writes)....... 163 29 Synchronous Read Cycle Timing ...................................................................... 165 30 Synchronous Write Cycle Timing ...................................................................... 166 31 Synchronous Service Acknowledge Cycle Timing ............................................ 167 32 Synchronous DMA Write Cycle Timing (Two Back-to-Back 3-Cycle DMA Writes) ......................................................... 168 33 Synchronous DMA Read Cycle Timing (Two Back-to-Back 3-Cycle DMA Reads) ......................................................... 168 34 UART to RS232 and IR Port Interface Motherboard Example Schematic ........ 172 |
Số phần tương tự - CD1284 |
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Mô tả tương tự - CD1284 |
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