Block Diagrams

MC13191 Technical Data, Rev. 1.3

Freescale Semiconductor

3

— RoHS compliant

— Meets moisture sensitivity level (MSL) 3

— 260 °C peak reflow temperature

— Meets lead-free requirements

3 Block Diagrams

Figure 2 shows a simplified block diagram of the MC13191 transceiver that meets the requirements of the

IEEE 802.15.4 PHY. Figure 3 shows the basic system block diagram for the MC13191 in an application.

Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request line. The

media access control (MAC), drivers, and network and application software (as required) reside on the

host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor

depending on application requirements.

4 Data Transfer Mode

The MC13191 has a data transfer mode called Packet Mode where data is buffered in on-chip Packet

RAMs. There is a TX Packet RAM and an RX Packet RAM, each of which are 64 locations by 16 bits

wide.

4.1 Packet Structure

Figure 4 shows the packet structure of the MC13191 which is consistent with the IEEE 802.15.4 Standard.

Payloads of up to 125 bytes are supported. The MC13191 adds a four-byte preamble, a one-byte Start of

Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A two-byte Frame

Check Sequence (FCS) is calculated and appended to the end of the data.

4.2 Receive Path Description

In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals

through two down-conversion stages. An Energy Detect can be performed based upon the baseband energy

integrated over a specific time interval. The digital back end performs Differential Chip Detection (DCD),

the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset QPSK (O-QPSK) signal,

determines the symbols and packets, and detects the data.

The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in

RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the

transmitted data which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured

over a 64 µs period after the packet preamble and stored in RAM.

The MC13191 uses a packet mode where the data is processed as an entire packet and stored in Rx Packet

RAM. The MCU is notified that an entire packet has been received via an interrupt.