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54LS113 bảng dữ liệu(PDF) 1 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện 54LS113
Giải thích chi tiết về linh kiện  Dual JK Edge-Triggered Flip-Flop
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54LS113 bảng dữ liệu(HTML) 1 Page - National Semiconductor (TI)

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TLF10205
June 1989
54LS113
Dual JK Edge-Triggered Flip-Flop
General Description
The 54LS113 offers individual J K Set and Clock inputs
When the clock goes HIGH the inputs are enabled and data
may be entered The logic level of the J and K inputs may
be changed when the clock pulse is HIGH and the bistable
will perform according to the Truth Table as long as mini-
mum setup and hold times are observed Input data is trans-
ferred to the outputs on the falling edge of the clock pulse
Connection Diagram
Dual-In-Line Package
TLF10205 – 1
Order Number 54LS113DMQB
54LS113FMQB or 54LS113LMQB
See NS Package Number E20A J14A or W14B
Logic Symbol
TLF10205 – 2
VCC e Pin 14
GND e Pin 7
Truth Table
Inputs
Output
tn
tn a 1
JK
Q
LL
Qn
LH
L
HL
H
HH
Qn
tn e Bit Time before Clock Pulse
tn a 1 e Bit Time after Clock Pulse
H e HIGH Voltage Level
L e LOW Voltage Level
Asynchronous Input
Low input to SD sets Q to HIGH level
Set is independent of clock
Pin Names
Description
J1 J2 K1 K2
Data Inputs
CP1 CP2
Clock Pulse Inputs (Active Falling Edge)
SD1 SD2
Direct Set Inputs (Active LOW)
Q1 Q2 Q1 Q2
Outputs
C1995 National Semiconductor Corporation
RRD-B30M105Printed in U S A


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