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TL16C550DPT bảng dữ liệu(PDF) 5 Page - Texas Instruments

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TL16C550D, TL16C550DI
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLLS597C − APRIL 2004 − REVISED JUNE 2005
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
auto-CTS and auto-RTS functional timing
Start
Bits 0 − 7
Start
Bits 0 − 7
Start
Bits 0 − 7
Stop
Stop
Stop
SOUT
CTS
NOTES: A. When CTS is low, the transmitter keeps sending serial data out.
B. If CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does
not send the next byte.
C. When CTS goes from high to low, the transmitter begins sending data again.
Figure 2. CTS Functional Timing Waveforms
The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.
Start
Byte N
Start
Byte N+1
Start
Byte
Stop
Stop
Stop
SIN
RTS
RD1
(RD RBR)
12
N
N+1
NOTES: A. N = RCV FIFO trigger level (1, 4, or 8 bytes)
B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS section.
Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes
Byte 14
Byte 15
SIN
RTS
RD1
(RD RBR)
Start
Byte 18 Stop
Start
Byte 16
Stop
RTS Released After the
First Data Bit of Byte 16
NOTES: A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the
sixteenth byte.
B. RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more than
one byte of space available.
C. When the receive FIFO is full, the first receive buffer register read reasserts RTS.
Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes


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