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TL16C550DIPTR bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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TL16C550DIPTR bảng dữ liệu(HTML) 4 Page - Texas Instruments |
4 / 50 page TL16C550D, TL16C550DI ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL SLLS597C − APRIL 2004 − REVISED JUNE 2005 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 detailed description autoflow control (see Figure 1) Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a TLC16C550D with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds the receiver FIFO read latency. RCV FIFO Serial to Parallel Flow Control XMT FIFO Parallel to Serial Flow Control Parallel to Serial Flow Control Serial to Parallel Flow Control XMT FIFO RCV FIFO ACE1 ACE2 D7 − D0 SIN SOUT RTS CTS SOUT SIN CTS RTS D7 − D0 Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example auto-RTS (see Figure 1) Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram) and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of 1, 4, or 8 (see Figure 3), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register. When the trigger level is 14 (see Figure 4), RTS is deasserted after the first data bit of the 16th character is present on the SIN line. RTS is reasserted when the RCV FIFO has at least one available byte space. auto-CTS (see Figure 1) The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last stop bit that is currently being sent (see Figure 2). The auto-CTS function reduces interrupts to the host system. When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error may result. enabling autoflow control and auto-CTS Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to a 1. Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem control register must be cleared (this assumes that a control signal is driving CTS). |
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