LM2467 datasheet(5/43 Pages) NSC

tên linh kiện	LM2467

Giải thích chi tiết về linh kiện	150 MHz I2C Compatible RGB Preamplifier with Internal 254 Character OSD ROM, 512 Character RAM and 4 DACs

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DAC Output Electrical Characteristics

Unless otherwise noted: T

A = 25˚C, VCC = +5.0V, VIN = 0.7V, VABL =VCC,CL = 8 pF, Video Outputs = 2.0 VP-P. See (Note 7)

for Min and Max parameters and (Note 6) for Typicals. DAC parameters apply to all 4 DACs.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V

Min DAC

Min Output Voltage of DAC

Register Value = 0x00

0.5

0.7

V

Max DAC

Mode 00

Max Output Voltage of DAC

Register Value = 0xFF,

DCF[1:0] = 00b

4.2

V

Max DAC

Mode 01

Max Output Voltage of DAC in

DCF Mode 01

Register Value = 0xFF,

DCF[1:0] = 01b

2.35

V

∆V

Max DAC

(Temp)

DAC Output Voltage Variation

with Temperature

0 < T < 70˚C ambient

±0.5

mV/˚C

∆V

Max DAC (VCC)

DAC Output Voltage Variation

with V

CC

V

CC varied from 4.75V to 5.25V, DAC

register set to mid-range (0x7F)

50

mV

Linearity

Linearity of DAC over its Range

5

%

Monotonicity

Monotonicity of the DAC

Excluding Dead Zones

±0.5

LSB

I

MAX

Max Load Current

1.0

mA

System Interface Signal Characteristics

Unless otherwise noted: T

A = 25˚C, VCC = +5.0V, VIN = 0.7V, VABL =VCC,CL = 8 pF, Video Outputs = 2.0 VP-P. See (Note 7)

for Min and Max parameters and (Note 6) for Typicals. DAC parameters apply to all 4 DACs.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V

VTH+

VFLYBACK Positive Switching

Guarantee

Vertical Blanking triggered

2.0

V

SPOT

Spot Killer Voltage

Table 14,V

CC Adjusted to Activate

3.4

3.9

4.3

V

Ref

V

Ref Output Voltage (pin 2)

1.25

1.45

1.65

V

IL (SCL, SDA)

Logic Low Input Voltage

−0.5

1.5

V

IH (SCL, SDA)

Logic High Input Voltage

3.5

V

CC +

0.5

V

I

L (SCL, SDA)

Logic Low Input Current

SDA or SCL, Input Voltage = 0.4V

±10

µA

I

H (SCL, SDA)

Logic High Input Voltage

SDA or SCL, Input Voltage = 4.5V

±10

µA

V

OL (SCL, SDA)

Logic Low Output Voltage

I

O = 3 mA

0.5

V

f

H Min

Minimum Horizontal Frequency

PLL & OSD Functioning; PPL = 0

25

kHz

f

H Max

Maximum Horizontal Frequency

PLL & OSD Functioning; PPL = 4

110

kHz

I

HFB IN Max

Horizontal Flyback Input

Current Absolute Maximum during

Flyback

5mA

I

IN

Peak Current during Flyback

Design Value

4

mA

I

HFB OUT Max

Horizontal Flyback Input Current

Absolute Maximum during Scan

−700

µA

I

OUT

Peak Current during Scan

Not exact - Duty Cycle Dependent

−550

µA

I

IN THRESHOLD

I

IN H-Blank Detection Threshold

0

µA

t

H-BLANK ON

H-Blank Time Delay - On

+ Zero crossing of I

HFB to 50% of

output blanking start. I

24 = +1.5mA

45

ns

t

H-BLANK OFF

H-Blank Time Delay - Off

− Zero crossing of I

HFB to 50% of

output blanking end. I

24 = −100µA

85

ns

V

BLANK Max

Maximum Video Blanking Level

Test Setting 4, AC input signal

0

0.25

V

f

FREERUN

Free Run H Frequency, Including

H Blank

42

kHz

t

PW CLAMP

Minimum Clamp Pulse Width

See (Note 15)

200

ns

V

CLAMP MAX

Maximum Low Level Clamp

Pulse Voltage

Video Clamp Functioning

2.0

V

CLAMP MIN

Minimum High Level Clamp

Pulse Voltage

Video Clamp Functioning

3.0

V

I

CLAMP Low

Clamp Gate Low Input Current

V

23 = 2V

−0.4

µA

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