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STM706 bảng dữ liệu(PDF) 9 Page - STMicroelectronics |
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9 / 27 page 9/27 STM705/706/707/708/813L OPERATION Reset Output The STM705/706/707/708/813L Supervisor as- serts a reset signal to the MCU whenever VCC goes below the reset threshold (VRST), a watch- dog time-out occurs (if WDO is tied to MR), or when the Push-button Reset Input (MR) is taken low. RST is guaranteed to be a logic low (logic high for STM707/708/813L) for VCC < VRST down to VCC =1V for TA = 0°C to 85°C. During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for the reset time-out period, trec. After this interval RST returns high. If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays low for at least the reset time-out period (trec). Any time VCC goes below the reset threshold the internal timer clears. The reset timer starts when VCC returns above the reset threshold. Push-button Reset Input A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see Figure 31., page 21) after it returns high. The MR input has an internal 40k Ω pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/ collector outputs. Connect a normally open mo- mentary switch from MR to GND to create a man- ual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1µF capacitor from MR to GND to provide ad- ditional noise immunity. MR may float, or be tied to VCC when not used. Watchdog Input (STM705/706/813L) The watchdog timer can be used to detect an out- of-control MCU. If the MCU does not toggle the Watchdog Input (WDI) within tWD (1.6sec), the re- set is asserted. The internal 1.6sec timer is cleared by either: 1. a reset pulse, or 2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50ns. If WDI is tied high or low, a reset pulse is triggered every 1.8sec (tWD + trec), if WDO is connected to MR. See Figure 32., page 21 for STM705/706/813L. The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is re- leased, the timer starts counting. Note: The watchdog function may be disabled by floating WDI or tri-stating the driver connected to WDI. When tri-stated or disconnected, the maxi- mum allowable leakage current is 10uA and the maximum allowable load capacitance is 200pF. Watchdog Output (STM705/706/813L) When VCC drops below the reset threshold, WDO will go low even if the watchdog timer has not yet timed out. However, unlike the reset output, WDO goes high as soon as VCC exceeds the reset threshold. WDO may be used to generate a reset pulse by connecting it to the MR input. Power-fail Input/Output The Power-fail Input (PFI) is compared to an inter- nal reference voltage (independent from the VRST comparator). If PFI is less than the power-fail threshold (VPFI), the Power-Fail Output (PFO) will go low. This function is intended for use as an un- dervoltage detector to signal a failing power sup- ply. Typically PFI is connected through an external voltage divider (see Figure 10., page 8) to either the unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the STM705/706/707/708/ 813L or the microprocessor drops below the mini- mum operating voltage. If the comparator is unused, PFI should be con- nected to VSS and PFO left unconnected. PFO may be connected to MR on the STM703/704/818 so that a low voltage on PFI will generate a reset output. |
Số phần tương tự - STM706 |
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Mô tả tương tự - STM706 |
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