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LM2751 bảng dữ liệu(PDF) 4 Page - National Semiconductor (TI) |
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LM2751 bảng dữ liệu(HTML) 4 Page - National Semiconductor (TI) |
4 / 11 page Electrical Characteristics (Notes 2, 7) (Continued) Limits in standard typeface are for T A =25 oC. Limits in boldface type apply over the full operating ambient temperature range (-40˚C ≤ T A ≤ +85˚C) . Unless otherwise noted, specifications apply to the LM2751 Typical Application Circuit (pg. 1) with: V IN = 3.6V, V(EN) = V IN, CS0=CS1=VIN,C1 =C2 = 1.0µF, CIN =COUT = 2.2µF (Note 8). Symbol Parameter Conditions Min Typ Max Units fsw Switching Frequency CS0 = High, CS1 = Low 2.8V ≤ V IN ≤ 5.5V 6.7 (−30%) 9.5 12.3 (+30%) kHz CS0 = Low, CS1 = Low 2.8V ≤ V IN ≤ 5.5V 26 (−30%) 37 48 (+30%) CS0 = Low, CS1 = High 2.8V ≤ V IN ≤ 5.5V 210 (−30%) 300 390 (+30%) CS0 = High, CS1 = High 2.8V ≤ V IN ≤ 5.5V 508 (−30%) 725 942 (+30%) V IH Logic Input High Input Pins: EN, CS0, CS1 2.8V ≤ V IN ≤ 5.5V 1.00 V IN V V IL Logic Input Low Input Pins: EN, CS0, CS1 2.8V ≤ V IN ≤ 5.5V 0 .30 V I IH Logic Input High Current Input Pins: CS0, CS1 V(CSx) = 1.8V 10 nA Input Pin: EN V(EN) = 1.8V(Note 9) 2µA I IL Logic Input Low Current Input Pins: EN, CS0, CS1 V(EN, CSx) = 0V 10 nA V G Gain Transition Voltage (Version A, B) 1.5X to 2X 3.50 V 2X to 1.5X 3.58 Hysteresis 40 80 150 mV I SC Short Circuit Output Current V OUT = 0V 250 mA t ON V OUT Turn-On Time (Note 10) 300 µs Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ=150˚C (typ.) and disengages at TJ=140˚C (typ.). Note 4: The Human body model is a 100 pF capacitor discharged through a 1.5k Ω resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin. MIL-STD-883 3015.7 Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operation junction temperature (TJ-MAX-OP =115 oC), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX =TJ-MAX-OP -(θJA xPD-MAX). Note 6: Junction-to-ambient thermal resistance ( θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. The test board is a 4 layer FR-4 board measuring 102mm x 76mm x 1.6mm witha2x1 array of thermal vias. The ground plane on the board is 50mm x 50mm. Thickness of copper layers are 36µm/18µm /18µm/36µm (1.5oz/1oz/1oz/1.5oz). Ambient temperature in simulation is 22oC, still air. Power dissipation is 1W. The value of θJA of the LM2751 in LLP-10 could fall in a range as wide as 50oC/W to 150oC/W (if not wider), depending on PWB material, layout, and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note 1187: Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet. Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but represent the most likely norm. Note 8: CIN,COUT,C1, and C2: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. Note 9: EN Logic Input High Current (IIH)isdue toa1MΩ(typ.) pull-down resistor connected internally between the EN pin and GND. Note 10: Turn-on time is measured from when the EN signal is pulled high until the output voltage on VOUT crosses 90% of its final value. www.national.com 4 |
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