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STW81100

where:

– FVCO: output frequency of VCO.

– P: modulus of dual modulus prescaler.

– B: division ratio of the main counter.

– A: division ratio of the swallow counter.

– Fref: input reference frequency.

– R: division ratio of reference counter.

– N: division ratio of PLL

For a correct work of the VCO divider, B must be strictly higher than A. A can take any value ranging from

0 to 63. The range of the N number can vary from 4096 to 32767.

Figure 13. VCO Divider Diagram

7.5 Phase frequency detector (PFD)

The PFD takes inputs from the reference and the VCO dividers and produces an output proportional to

the phase error. The PFD includes a delay gate that controls the width of the anti-backlash pulse. This

pulse ensures that there is no dead zone in the PFD transfer function.

Figure 6 is a simplified schematic of the PFD.

Figure 14. PDF Diagram

Prescaler

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6 bit

A counter

9bit

B counter

To PFD

modulus

VCOBUF+

VCOBUF-

Prescaler

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6 bit

A counter

9bit

B counter

To PFD

modulus

VCOBUF+

VCOBUF-

D FF

R

Fref

VDD

R

D FF

Fref

VDD

Delay

Up

Down

ABL

D FF

R

Fref

VDD

R

D FF

Fref

VDD

Delay

Up

Down

ABL